PCA9543D PHILIPS [NXP Semiconductors], PCA9543D Datasheet - Page 11
![no-image](/images/no-image-200.jpg)
PCA9543D
Manufacturer Part Number
PCA9543D
Description
2-channel I2C switch with interrupt logic and reset
Manufacturer
PHILIPS [NXP Semiconductors]
Datasheet
1.PCA9543D.pdf
(15 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PCA9543D
Manufacturer:
PHI
Quantity:
20 000
1. Pass gate propagation delay is calculated from the 20
2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH
3. C
Philips Semiconductors
AC CHARACTERISTICS
NOTES:
2004 Oct 01
INT
SYMBOL
t
t
t
2-channel I
t
t
t
t
VD:DATH
t
RESET
t
VD:DATL
REC:STA
t
the undefined region of the falling edge of SCL.
SU;STO
VD:ACK
HD;STA
SU;STA
HD;DAT
SU;DAT
WL(rst)
t
t
H
f
t
HIGH
L
LOW
b
SCL
BUF
t
t
C
t
t
SP
t
pd
t
t
pwr
rst
pwr
R
iv
F
ir
= total capacitance of one bus line in pF.
b
SDA
SCL
Propagation delay from SDA to SD
SCL clock frequency
Bus free time between a STOP and START condition
Hold time (repeated) START condition
After this period, the first clock pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
Setup time for a repeated START condition
Setup time for STOP condition
Data hold time
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Capacitive load for each bus line
Pulse width of spikes which must be suppressed
by the input filter
Data valid (HL)
Data valid (LH)
Data valid Acknowledge
INTn to INT active valid time
INTn to INT inactive delay time
LOW-level pulse width rejection or INTn inputs
HIGH-level pulse width rejection or INTn inputs
Pulse width LOW reset
Reset time (SDA clear)
Recovery to Start
P
t
BUF
2
C switch with interrupt logic and reset
S
t
HD;STA
t
LOW
PARAMETER
t
t
Figure 13. Definition of timing on the I
R
HD;DAT
n
or SCL to SC
typical R
t
HIGH
n
ON
t
F
11
and and the 15 pF load capacitance.
t
SU;DAT
STANDARD-MODE
MIN
250
500
500
4.7
4.0
4.7
4.0
4.7
4.0
—
0
—
—
—
—
—
—
—
—
—
0
1
4
0
2
I
2
C-BUS
2
C-bus
Sr
MAX
1000
3.45
0.3
100
300
400
0.6
50
—
—
—
—
—
—
—
—
—
—
—
—
t
1
1
4
2
SU;STA
1
t
HD;STA
min
20 + 0.1C
20 + 0.1C
of the SCL signal) in order to bridge
MIN
100
500
500
1.3
0.6
1.3
0.6
0.6
0.6
—
0
—
—
—
—
—
—
—
0
1
4
0
FAST-MODE
2
t
I
SP
2
C-BUS
b
b
3
3
t
SU;STO
PCA9543
MAX
0.3
400
300
300
400
Product data sheet
0.9
0.6
50
—
—
—
—
—
—
—
—
—
—
—
—
1
1
4
2
1
SU00645
P
UNIT
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s
s
s
s
s