AS8530-ASOT AMSCO [austriamicrosystems AG], AS8530-ASOT Datasheet - Page 13

• Manufacturer Part Number: AS8530-ASOT
• Description: LIN Transceiver with Integrated Voltage Regulator and MCU Interface for Automotive Applications
• Manufacturer: AMSCO [austriamicrosystems AG]

AS8530
Preliminary Data Sheet - D e t a i l e d D e s c r i p t i o n
Figure 4. Reset Functionality
7.1.5
The POR-VCC generates RESET_VCC_N signal as output which determines under-voltage reset of the output of the LDO. The rising edge of
the V
control the RESET output. When V
level to high level and pin RESET is inactive (high). If V
RESET_VCC_N switches from high level to low level and pin RESET is active (low). The RESET_VCC_N signal is used to initializes Window
watchdog timer, TX time-out, Test control circuits, 2-wire SP, and logic associated with SP (everything other than the SP control registers). V
under-voltage reset threshold voltage level adjustment can be made by 2 bit OTP as explained in OTP interface.
7.1.6 Window Watchdog (WWD)
To keep the external microcontroller always in proper function state, a window watchdog circuit is implemented. The WWD trigger is generated
by external MCU through SP interface. If the window is missed, a reset on the RESET pin with certain reset time (t
function can be enabled or disabled by factory setting. The watchdog is started after the ASSP exits reset. Under normal working conditions,
microcontroller gives a WWD trigger every time in the window period of WD_TSV (service time). If the trigger does not occur during WD_TSV or
occurs too early during WD_TCL (non-service time), then RESET output is pulled low (active), which will reset the micro-controller. WWD circuit
is turned on after the RESET pin goes back to high (inactive). If V
enabled, there is a 3-bit factory programming available to set the trigger window.
Figure 5. Window Watchdog Trigger
www.austriamicrosystems.com/Lin_CompanionIC/AS8530
RESET
VSUP
VCC
CC
V
gives an under-voltage reset “off” and the falling edge of the V
Trigger via
CC
SPI
VUVR_ON
VUVR_OF
Undervoltage Reset
F
Initialisation
t
Res
Last trigger point
CC
T>Tj
rises up Vuvr_off for a period greater than reset duration (tRes) then RESET_VCC_N switches from low
Thermal shutdown
Trigger
restart
period
t
rr
Non-Service tim e (W D_TCL)
Unwanted trigger point
(System will be
RESET)
T<Tj
t
Res
CC
falls below Vuvr_on for a period greater than a predetermined delay (trr) then
CC
Spike VSUP
Revision 0.01
t<t
Earliest possible
trigger point
(System will not
RESET)
< Vuvr_on, WWD circuit is switched off. When the WWD function is
rr
CC
Period
gives an under-voltage reset “on”. This under-voltage signal is used to
50 %
Service tim e (W D_TSV )
Low voltage VSUP
Valid Trigger point
(System will not be
RESET)
t
Res
WATCHDOG
latest possible
trigger point
(System wil not be
RESET)
MISSING
ACCESS
t
Res
100 %
Res
) is generated. The WWD
Current limitation active
t
Res
13 - 29
CC