ADV7302A AD [Analog Devices], ADV7302A Datasheet
ADV7302A
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ADV7302A Summary of contents
Page 1
... It includes six high speed video D/A converters with TTL compatible inputs. The ADV7302A/ADV7303A has three separate 8-bit wide input ports that accept data in high definition and/or standard defini- tion video format. For all standards, external horizontal, vertical, ...
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... HD High Definition Video, i.e., Progressive Scan or HDTV. PS Progressive Scan Video, conforming to SMPTE293M or ITU-R.BT1358. SSAF is a trademark of Analog Devices, Inc. *ADV7302A Only Macrovision Rev 1.0 (525 p/625 p)* CGMS-A (525 p) Standard Definition Programmable Features 8 Oversampling (108 MHz) Internal Test Pattern Generator (Color Bars, Black Bar) ...
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... ADV7302A/ADV7303A–SPECIFICATIONS ( 2.375 V–2.625 2.375 V–3.600 DD_IO Parameter 1 STATIC PERFORMANCE Resolution Integral Nonlinearity 2 Differential Nonlinearity, +ve 2 Differential Nonlinearity, –ve DIGITAL OUTPUTS Output Low Voltage Output High Voltage Three-State Leakage Current Three-State Output Capacitance ...
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... ADV7302A/ADV7303A DYNAMIC SPECIFICATIONS Parameter PROGRESSIVE SCAN MODE Luma Bandwidth Chroma Bandwidth SNR SNR SNR HDTV MODE Luma Bandwidth Chroma Bandwidth SNR SNR SNR STANDARD DEFINITION MODE Hue Accuracy Color Saturation Accuracy Chroma Nonlinear Gain Chroma Nonlinear Phase Chroma/Luma Intermod Chroma/Luma Gain Ineq ...
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... ADV7302A/ADV7303A = 1.235 760 , R REF SET LOAD Unit Test Conditions kHz µs µs µs First Clock Generated After This Period µs Relevant for Repeated Start Condition µ MHz ...
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... ADV7302A/ADV7303A CLKIN_A P_HSYNC, CONTROL P_VSYNC, I/PS P_BLANK Y7–Y0 C7–C0 CONTROL S_HSYNC, O/PS S_VSYNC CLOCK HIGH TIME, = CLOCK LOW TIME Figure 2. HD 4:2:2 Input Data Format Timing Diagram, Input Mode: PS Input Only, HDTV Input Only (Input Mode at Subaddress 01h = 001 or 010) CLKIN_A P_HSYNC, ...
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... Cb0 Y0 Cr0 CLOCK LOW TIME, = DATA SETUP TIME 8-Bit Interleaved @ 27 MHz, Input Mode: PS Input Only (Input –7– ADV7302A/ADV7303A Gxxx Gxxx Bxxx Bxxx Rxxx Rxxx Crxxx Yxxx DATA HOLD TIME ...
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... ADV7302A/ADV7303A CLKIN_A P_HSYNC, CONTROL P_VSYNC, I/PS P_BLANK Y7–Y0 CONTROL S_HSYNC, O/PS S_VSYNC CLOCK HIGH TIME, = CLOCK LOW TIME Figure 6. PS 4:2:2 1 Mode at Subaddress 01h = 111) CLKIN_A t 9 S_HSYNC, CONTROL S_VSYNC, I/PS S_BLANK S7–S0 Cb CONTROL S_HSYNC, O/PS S_VSYNC Figure 7. 8-Bit SD Pixel Input Timing Diagram, Input Mode: SD Input Only (Input Mode at Subaddress 01h = 000) ...
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... Subaddress 01h = 011, 101, or 110) REV Cb0 Cr0 Cb2 Cr2 Cr0 Cb2 Cb4 Cr0 Cb1 t 11 –9– ADV7302A/ADV7303A IN SLAVE MODE Y2 Y3 Cr2 IN MASTER/SLAVE MODE WITH EAV/SAV HD INPUT Y5 Cr4 SD INPUT Y2 ...
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... ADV7302A/ADV7303A CLKIN_B P_HSYNC, CONTROL P_VSYNC, I/PS P_BLANK Cb0 Y7– CLKIN_A t S_HSYNC, CONTROL S_VSYNC, I/PS S_BLANK S7–S0 Cb0 Figure 10. SD and HD Simultaneous Input, Input Mode: SD and PS 8-Bit (Input Mode at Subaddress 01h = 100) P_HSYNC P_VSYNC P_BLANK Y7– CLKCYCLES FOR 525p CLKCYCLES FOR 625p AS RECOMMENDED BY STANDARD Figure 11 ...
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... Figure 12. HD Input Timing Diagram CLOCK/2 CLOCK/2 Figure 13. SD Timing Input for Timing Mode Figure 14. MPU Port Timing Diagram –11– ADV7302A/ADV7303A Cr0 Cr1 Cr2 Cr3 Cb0 Cb1 Cb2 Cb3 PAL = 132 ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7302A/ADV7303A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Multifunctional Input: Realtime Control (RTC) Input, Timing Reset Input, and Subcarrier Reset Input Pixel Clock Input for HD Only or SD Only Modes This input resets the on-chip timing generator and sets the ADV7302A/ ADV7303A into default register setting. Reset is an active low signal. External Loop Filter for the internal PLL A 760 Ω ...
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... Logic Level “1” corresponds to a read operation, while Logic Level “0” corresponds to a write operation set by setting the ALSB Pin of the ADV7302A/ADV7303A to Logic Level “0” or Logic Level “1.” When ALSB is set to “1,” there is ...
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... P = STOP BIT REGISTER ACCESSES The MPU can write to or read from all of the registers of the ADV7302A/ADV7303A except the subaddress registers that are write-only registers. The subaddress register determines which register the next read or write operation accesses. All communica- tions with the part through the bus start with an access to the subaddress register ...
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... ADV7302A/ADV7303A Subaddress Register 00h Power Mode Register NOTES When enabled, the current consumption is reduced to µA level. All DACs and the internal PLL cct are disabled This control allows the internal PLL circuit to be powered down and the oversampling to be switched off. ...
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... –17– ADV7302A/ADV7303A Reset 0 0 Zero must be written 20h to these bits. 0 Disabled 1 Enabled. 0x11h, Bit 2 must also be enabled. 0 Disable Programmable RGB Matrix 1 Enable Programmable RGB Matrix No SYNC SYNC on all RGB Outputs ...
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... ADV7302A/ADV7303A Subaddress Register 10h HD Mode Register 1 11h HD Mode Register 2 12h HD Mode Register 3 Table IV. HD Mode Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting HD Output Standard HD Input Control Signals HD 625 720 BLANK Polarity ...
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... HD RGB Input HD Sync on PrPb HD Color DAC Swap 2 HD Gamma Curve A Gamma Curve Enable Adaptive Filter Mode Adaptive Filter Enable 0 1 –19– ADV7302A/ADV7303A Reset 0 Cb after Falling 4Ch Edge of HSYNC 1 Cr after Falling Edge of HSYNC. 0 Reserved 0 Reserved 0 Disabled 1 Enabled ...
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... ADV7302A/ADV7303A Subaddress Register 16h HD Y Color 17h HD Cr Color 18h HD Cb Color 19h Reserved 1Ah Reserved 1Bh Reserved 1Ch Reserved 1Dh Reserved 1Eh Reserved 1Fh Reserved 20h HD Sharpness Filter Gain 21h HD CGMS Data 0 22h HD CGMS Data 1 23h HD CGMS Data 2 24h HD Gamma A ...
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... HD Adaptive Filter Threshold A Value HD Adaptive Filter Threshold B Value HD Adaptive Filter Threshold C Value –21– ADV7302A/ADV7303A Reset Gain 00hex Gain Gain Gain A = –8 ...
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... ADV7302A/ADV7303A Subaddress Register 3Eh Reserved 3Fh Reserved 40h SD Mode Register 0 41h Reserved 42h SD Mode Register 1 Table VII. SD Mode Registers Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting SD Standard SD Luma Filter Chroma Filter ...
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... SD Color Bars 0 1 Reserved Scale SD Y Scale SD Hue Adjust SD Brightness SD Luma SSAF Gain 0 1 Reserved 0 Reserved 0 Reserved 0 –23– ADV7302A/ADV7303A Reset 0 No Pedestal on YUV 00h 1 7.5 IRE Pedestal on YUV 700 mV/300 714 mV/286 700 mV p-p [PAL]; 1000 mV p-p [NTSC 700 mV p-p ...
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... ADV7302A/ADV7303A Subaddress Register 48h SD Mode Register 5 49h SD Mode Register 6 *For more detail, see Input and Output Configuration section. Table VII. SD Mode Registers (continued) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting Reserved Reserved SD Double Buffering SD Input Format ...
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... –25– ADV7302A/ADV7303A Reset 0 Slave Mode 08h 1 Master Mode 0 0 Mode Mode Mode Mode 3 Enabled Disabled No Delay 2 Clock Cycles 4 Clock Cycles 6 Clock Cycles –40 IRE –7.5 IRE ...
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... ADV7302A/ADV7303A Subaddress Register 59h SD CGMS/WSS 0 5Ah SD CGMS/WSS 1 5Bh SD CGMS/WSS 2 5Ch SD LSB Register 5Dh SD Y Scale Register 5Eh SD V Scale Register 5Fh SD U Scale Register 60h SD Hue Register 61h SD Brightness/WSS 62h SD Luma SSAF 63h SD DNR 0 Table VIII. SD Registers (continued) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting ...
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... SD Gamma Curve B Data Points SD Gamma Curve B Data Points Field Count Reserved Reserved 0 Reserved 0 Reserved Code X X –27– ADV7302A/ADV7303A Reset 00h Pixels 4 Pixels 8 Pixels 16 Pixels ...
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... Macrovision 8Dh Macrovision 8Eh Macrovision 8Fh Macrovision 90h Macrovision 91h Macrovision *Macrovision Registers are only available on the ADV7302A. Table VIII. SD Registers (continued) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting Timing Reset Reserved Reserved Reserved Reserved 0 Reserved ...
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... S_HSYNC DECODER S_BLANK 27MHz CLKIN_A YCrCb 8 S7–S0 CrCb 8 C7– Y7–Y0 INTERLACED TO P_VSYNC PROGRESSIVE 3 P_HSYNC P_BLANK 27MHz CLKIN_B ADV7302A/ ADV7303A S_VSYNC 3 S_HSYNC S_BLANK SDTV DECODER 27MHz CLKIN_A YCrCb 8 S7–S0 HDTV DECODER CrCb 8 C7–C0 1080 720 p Y7–Y0 ...
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... For correct color decoding, the Pixel Align Bit [Subaddress 01h] must then be set to “l” after a delay of one field. The ADV7302A/ADV7303A is now in free run mode, any changes in the timing information are ignored. CLKIN_A ...
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... YCrCb Y7–Y0 [MSB = Y7] 8 4:2:2 YCrCb S7–S0 [MSB = S7] 4:2:2 Y Y7–Y0 [MSB = Y7] CrCb C7–C0 [MSB = C7] –31– ADV7302A/ADV7303A Subaddress Register Setting 01h, 48h 00h, 00h 01h, 48h 00h, 08h 01h, 13h 10h, 40h 01h, 13h 70h, 40h 01h, 13h 10h, 40h 01h, 13h ...
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... ADV7302A/ADV7303A OUTPUT CONFIGURATION Tables XI–XIII demonstrate what output signals are assigned to the DACs when corresponding control bits are set. RGB/YUV O/P SD DAC O/P 1 Addr 02h, Bit 5 Addr 42h, Bit I/P HD RGB I/P RGB/YUV O/P Format Addr 15h, Bit 1 ...
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... ADV7302A/ADV7303A. Timing control signals for HSYNC, VSYNC, and BLANK have to be programmed by the user. Macrovision is not available in Async Timing Mode. Figure 28 shows an example of how to program the ADV7302A/ ADV7303A to accept a different high definition standard other than SMPTE293M, SMPTE274M, SMPTE296M, or ITU-R.BT1358 standards. ...
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... RTC TIME SLOT 01 NOTES 1 i.e., VCR OR CABLE 2 F PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7302A/ADV7303A F SC PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7302A/ADV7303A. 3 PAL LINE NORMAL LINE INVERTED; NTSC CHANGE 4 RESET ADV7302A/ADV7303A DDS ...
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... VERTICAL BLANKING INTERVAL The ADV7302A/ADV7303A accepts input data that contains VBI data [CGMS, WSS, VITS, etc and HD Modes. For SMPTE293M (525 p) standards, VBI data can be inserted on Lines each frame, or Lines for ITU-R.BT1358 (625 p) standard. For SD NTSC this data can be present on Lines 10 to 20, in PAL on Lines 7 to 22. If VBI is disabled [Address 11h, Bit 4 for HD ...
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... HD chroma SSAFs on the ADV7302A/ADV7303A. This filter has pass-band response and prevents signal components from being folded back into the frequency band. In 4:4:4 Input Mode, the video data is already interpolated by the external input device and the chroma SSAFs of the ADV7302A/ ADV7303A are bypassed. 0 –10 – ...
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... Figure 39. UV – HDTV 2 –10 –20 –30 –40 –50 –60 –70 – 100 110 Figure 40. UV – –37– ADV7302A/ADV7303A FREQUENCY – MHz Oversampling Filter, Pass Band FREQUENCY – ...
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... I C. The variation of frequency responses can be seen in Figures 41–59. In addition to the chroma filters listed above, the ADV7302A/ ADV7303A contains an SSAF filter specifically designed for and applicable to the color difference component outputs U and V. This filter has a cutoff frequency of approximately 2.7 MHz and – 3.8 MHz, as shown in Figure 41. This filter can be controlled via Address 42h, Bit 0 ...
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... Figure 47. Luma SSAF Filter MHz –10 – Figure 48. Luma SSAF Filter, Programmable Responses 100 110 Figure 49. Luma SSAF Filter, Programmable Gain –39– ADV7302A/ADV7303A FREQUENCY – MHz –2 –4 –6 – ...
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... ADV7302A/ADV7303A 1 0 –1 –2 –3 –4 – FREQUENCY – MHz Figure 50. Luma SSAF Filter, Programmable Attenuation 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz Figure 51. Luma CIF LP Filter 0 –10 –20 –30 –40 –50 –60 –70 ...
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... REV –10 –20 –30 –40 –50 –60 – –10 –20 –30 –40 –50 –60 – –41– ADV7302A/ADV7303A FREQUENCY – MHz Figure 58. Chroma CIF LP Filter FREQUENCY – MHz Figure 59. Chroma QCIF LP Filter ...
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... Address 08h: 92h Address 09h: 7Ch ) ( ) + × 0722 . B ' When the programmable RGB matrix is not functional, the ADV7302A/ADV7303A automatically scales YCrCb inputs to ) − all standards supported. For SMPTE293M, the register values are as follows: ) − Address 03h: 03h Address 04h: 1Eh ...
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... The ADV7302A/ADV7303A provides a range of ± 22.5° in increments of 0.17578125°. For normal operation (zero adjustment), this register is set to 80h. FFh and 00h represent the attainable upper and lower limit (respectively) of adjustment ...
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... ADV7302A/ADV7303A Gamma Correction [Subaddresses 21h–37h for HD; Subaddresses 66h–79h for SD] Gamma correction is available for SD and HD video. For each standard there are 20 8-bit wide registers. They are used to program the gamma correction curves A and B. HD Gamma Curve A is programmed at Addresses 24h–2Dh, HD Gamma Curve B at 2Eh– ...
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... Figure 62. Signal Input (Ramp) and Selectable Gamma Output HD SHARPNESS FILTER CONTROL AND ADAPTIVE FILTER CONTROL [Subaddresses 20h and 38h-3Dh] There are three filter modes available on the ADV7302A/ ADV7303A: Sharpness Filter Mode and two adaptive filter modes. HD Sharpness Filter Mode To enhance or attenuate the Y signal in the frequency ranges ...
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... ADV7302A/ADV7303A Figure 64. HD Sharpness Filter Control with Different Gain Settings for HD Sharpness Filter Gain Value HD Sharpness Filter and Adaptive Filter Application Examples HD Sharpness Filter Application The HD sharpness filter can be used to enhance or attenuate the Y video output signal. The register settings in Tables XIX and XX are used to achieve the results shown in Figure 64 ...
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... SHARPNESS MODE NOISE SIGNAL PATH INPUT FILTER BLOCK Y DATA INPUT MAIN SIGNAL PATH Figure 68. DNR Block Diagram –47– ADV7302A/ADV7303A 16 pixels for DNR CONTROL BLOCK SIZE CONTROL BORDER AREA BLOCK OFFSET GAIN CORING GAIN DATA CORING GAIN BORDER FILTER SUBTRACT SIGNAL ...
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... ADV7302A/ADV7303A The Digital Noise Reduction Registers are three 8-bit wide registers. They are used to control the DNR processing. Coring Gain Border [Address 63h, Bits 3–0] These four bits are assigned to the gain factor applied to border areas. In DNR Mode, the range of gain values is 0–1, in incre- ments of 0 ...
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... AD8061. More information on line driver buffering circuits is given in the relevant op amp data sheets. An optional analog reconstruction LPF might be required as an antialias filter if the ADV7302A/ADV7303A is connected to a device that requires this filtering. The filter specifications vary with the application, see Table XXIII. ...
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... The ADV7302A/ADV7303A is optimally designed for lowest noise performance, both radiated and conducted noise. To complement the excellent noise performance of the ADV7302A/ADV7303A imperative that great care be given to the PC board layout and the ADV7302A/ADV7303A power and ground lines. This BNC O/P 75R can be achieved by shielding the digital inputs and providing good decoupling ...
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... UNUSED INPUTS SHOULD BE GROUNDED REV. A the high clock rates used, long clock lines to the ADV7302A/ ADV7303A should be avoided to minimize noise pickup. Any active pull-up termination resistors for the digital inputs should be connected to the digital power plane and not the analog power plane ...
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... Bits C/W05 and C/W06 control whether or not CGMS data is output on odd and even fields. CGMS data can only be transmitted when the ADV7302A/ADV7303A is config- ured in NTSC mode. The CGMS data is 20 bits long, the function of each of these bits is as shown below. The CGMS data is preceded by a reference pulse of the same amplitude and duration as a CGMS bit, see Figure 81 ...
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... The ADV7302A/ADV7303A supports Wide Screen Signaling (WSS) conforming to the standard. WSS data is transmitted on Line 23. WSS data can only be transmitted when the ADV7302A/ ADV7303A is configured in PAL Mode. The WSS data is 14 bits long. The function of each of these bits is as shown in Table XXV. ...
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... Line 284. The data for this operation is stored in the SD Closed Captioning Registers [Addresses 51h–52h]. All clock run-in signals and timing to support closed captioning on Lines 21 and 284 are generated automatically by the ADV7302A/ 50 IRE 40 IRE REFERENCE COLOR BURST FREQUENCY = F ADV7303A ...
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... Appendix D TEST PATTERNS The ADV7302A/ADV7303A can generate SD and HD test patterns. Figure 84. NTSC Color Bars Figure 85. NTSC Black Bar (–21 mV, 0 mV, +3.5 mV, +7 mV, +10.5 mV, +14 mV, +18 mV, +23 mV) Figure 86. 525 p Hatch Pattern REV. A ADV7302A/ADV7303A Figure 87. PAL Color Bars Figure 88. PAL Black Bar (–21 mV, 0 mV, +3.5 mV, +7 mV, +10 ...
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... ADV7302A/ADV7303A Figure 90. 525 p Field Pattern Figure 91. 525 p Black Bar (–35 mV, 0 mV, +7 mV, +14 mV, +21 mV, +28 mV, +35 mV) Figure 92. 625 p Field Pattern Figure 93. 625 p Black Bar (–35 mV, 0 mV, +7 mV, +14 mV, +21 mV, +28 mV, +35 mV) –56– REV. A ...
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... Table XXX. PAL Black Bar Pattern Output on DAC A Subaddress Register Setting 40h 11h 4Ch CBh 4Dh 8Ah 4Eh 09h 4Fh 2Ah REV. A ADV7302A/ADV7303A Table XXXI. 525 p Hatch Pattern on DAC D Subaddress Register Setting 00h 12h 01h 10h 02h 20h 10h 40h 11h 05h ...
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... ADV7302A/ADV7303A Appendix E SD TIMING MODES [Subaddress 4Ah] Mode 0 (CCIR-656): Slave Option (Timing Register 0 TR0 = The ADV7302A/ADV7303A is controlled by the start active video (SAV) and end active video (EAV) time codes in the pixel data. All ANALOG VIDEO Y INPUT PIXELS ...
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... REV. A VERTICAL BLANK ODD FIELD VERTICAL BLANK 318 313 314 315 316 317 EVEN FIELD Figure 96. SD Master Mode 0, PAL Figure 97. SD Master Mode 0 Data Transitions –59– ADV7302A/ADV7303A DISPLAY DISPLAY 335 336 319 320 334 ...
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... HSYNC BLANK ODD FIELD FIELD retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7302A/ADV7303A automatically blanks all normally blank lines as per CCIR-624. HSYNC is input on the S_HSYNC Pin, BLANK on the S_BLANK Pin, and FIELD on the S_VSYNC Pin. VERTICAL BLANK ...
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... Mode 1: Master Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = this mode the ADV7302A/ADV7303A can generate horizon- tal SYNC and odd/even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame, i.e., HSYNC FIELD PAL = 12 NTSC = 16 BLANK ...
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... ODD FIELD A VSYNC low transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7302A/ADV7303A auto- matically blanks all normally blank lines as per CCIR-624. HSYNC is input on the S_HSYNC Pin, BLANK on the S_BLANK Pin, and FIELD on the S_VSYNC Pin ...
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... Mode 2: Master Option HSYNC, VSYNC, BLANK (Timing Register 0 TR0 = this mode the ADV7302A/ADV7303A can generate horizon- tal and vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd HSYNC VSYNC PAL = 12 ...
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... Mode 3: Master/Slave Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = this mode the ADV7302A/ADV7303A accepts or generates horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input when HSYNC is high indicates a new frame, DISPLAY ...
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... INPUT CODE 1023 OUTPUT VOLTAGE +350mV VIDEO ACTIVE 0mV 64 –300mV –350mV Figure 110. Output Levels for Full Input Selection –65– ADV7302A/ADV7303A EIA-770.3, STANDARD FOR Y OUTPUT VOLTAGE +700mV VIDEO ACTIVE +300mV 0mV –300mV EIA-770.3, STANDARD FOR Pr/Pb OUTPUT VOLTAGE +350mV +300mV ...
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... ADV7302A/ADV7303A Appendix G VIDEO STANDARDS SMPTE274M ANALOG WAVEFORM 4T EAV CODE INPUT PIXELS CLOCK SAMPLE NUMBER 2112 2116 2156 FVH* = FVH AND PARITY BITS SAV/EAV: LINE 1–562 SAV/EAV: LINE 563–1125 SAV/EAV: LINE1–20; 561–583; 1124–1125 SAV/EAV: LINE 21– ...
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... Figure 115. SMPTE296M (720 p) VERTICAL BLANKING INTERVAL VERTICAL BLANKING INTERVAL 563 564 565 566 567 568 569 Figure 116. SMPTE274M (1080 i) –67– ADV7302A/ADV7303A ACTIVE VIDEO ACTIVE VIDEO DISPLAY ...
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... ADV7302A/ADV7303A 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90 CCW Revision History Location 11/02—Data Sheet changed from REV REV. A. Changes to Figure Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Changes to TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Added Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Changes to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Changes to Table Changes to Table XII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Changes to Table XIII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Changes to the Realtime Control, Subcarrier Reset, Timing Reset section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Changes to SD SUBCARRIER FREQUENCY REGISTERS [Subaddress 4Ch– ...