AD8421 AD [Analog Devices], AD8421 Datasheet - Page 26

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AD8421

Manufacturer Part Number
AD8421
Description
3 nV/?Hz, Low Power
Manufacturer
AD [Analog Devices]
Datasheet

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AD8421
DRIVING AN ADC
The Class AB output stage, low noise and distortion, and high
bandwidth and slew rate make the
driving an ADC in a data acquisition system that requires front-
end gain, high CMRR, and dc precision. Figure 71 shows the
AD8421, in a gain-of-10 configuration, driving the AD7685,
a 16-bit, 250 kSPS pseudodifferential SAR ADC. The RC low-pass
filter that is shown between the
several purposes. It isolates the amplifier output from excessive
loading from the dynamic ADC inputs, reduces the noise
bandwidth of the amplifier, and provides overload protection for
the
empirically. To achieve the best ac performance, keep the impe-
dance magnitude greater than 1 kΩ at the maximum input signal
AD7685
analog inputs. The filter cutoff can be determined
±250mV
2.5V
10µF
1.1kΩ
AD8421
+IN
–IN
AD8421
AD8421
+12V
–12V
5kΩ
+12V
Figure 72. Typical Spectrum of the
and the
G = 10
–100
–120
–140
–160
a good choice for
–20
–40
–60
–80
REF
0
ADR435
0
AD7685
100Ω
+5V
3nF
Figure 71.
25
0.1µF
has
Rev. 0 | Page 26 of 28
10kΩ
10kΩ
AD8421
FREQUENCY (kHz)
50
IN+
IN–
2.5V
AD8421
GND
Driving an ADC
REF
10Ω
frequency, and set the filter cutoff to settle to ½ LSB in one
sampling period for a full-scale step. For additional considerations,
refer to the data sheet of the ADC in use.
In a gain-of-10 configuration, the
8 nV/√Hz voltage noise RTI (See the Calculating the Noise of
the Input Stage section.) The front-end gain makes the system
ten times more sensitive to input signals, with only a 7.5 dB
reduction of SNR. The high current output and load regulation
of the
reference without the need to provide another analog supply rail.
The reference pin buffer may be any low power, unity-gain stable,
dc precision op amp with less than approximately 25 nV/√Hz of
wideband noise, such as the OP1177. Not all proper decoupling is
shown in Figure 71. Take care to follow decoupling guidelines for
both amplifiers and the ADR435.
75
AD7685
(G = 10) Driving the
VDD
ADR435
SNR 81.12dB
THD –100.91dB
SFDR 90.71dB
VIO
100
SDO
SCK
CNV
SDI
1µF
allow the
AD7685
125
AD7685
3- OR 4-WIRE INTERFACE
AD8421
to be powered directly from the
has approximately
Data Sheet

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