ADV7400ABSTZ-1101 AD [Analog Devices], ADV7400ABSTZ-1101 Datasheet - Page 5

• Manufacturer Part Number: ADV7400ABSTZ-1101
• Description: 10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer
• Manufacturer: AD [Analog Devices]

TIMING CHARACTERISTICS
A
otherwise noted.
Table 3. Timing Characteristics
Parameter
SYSTEM CLOCK AND CRYSTAL
I
RESET FEATURE
CLOCK OUTPUTS
DATA and CONTROL OUTPUTS
DATA and CONTROL INPUTS
1
2
3
4
5
2
The min/max specifications are guaranteed over this range.
Temperature range T
Guaranteed by characterization.
Maximum LLC1 frequency is 80 MHz for the ADV7400AKSTZ-80.
DDR timing specifications depend on LLC1 output pixel clock; T
C® PORT
VDD
Crystal Nominal Frequency
Crystal Frequency Stability
Horizontal Sync Input Frequency
LLC1 Frequency Range
SCLK Frequency
SCLK Min Pulse Width High
SCLK Min Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDA Setup Time
SCLK and SDA Rise Time
SCLK and SDA Fall Time
Setup Time for Stop Condition
Reset Pulse Width
LLC1 Mark Space Ratio
Data Output Transition Time (SDP)
Data Output Transition Time (SDP)
Data Output Transition Time (CP)
Data Output Transition Time (CP)
Data Output Transition Time DDR (CP)
Data Output Transition Time DDR (CP)
Data Output Transition Time DDR (CP)
Data Output Transition Time DDR (CP)
Input Setup Time
Input Hold Time
= 3.15 V to 3.45 V, D
MIN
to T
MAX
4
VDD
: −40°C to +85°C.
= 1.65 V to 2.0 V, D
1, , 2 3
5
5
5
5
Symbol Test Conditions
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
19
20
:t
10
VDDIO
Negative clock edge to start of valid data
End of valid data to negative clock edge
End of valid data to negative clock edge
Negative clock edge to start of valid edge
Positive clock edge to end of valid data
Start of valid data to positive clock edge
Negative clock edge to end of valid data
Start of valid data to negative clock edge
HS_IN, VS_IN
DE_IN, data inputs
HS_IN, VS_IN
DE_IN, data inputs
LCC1
= 3.0 V to 3.6 V, P
/4 = 9.25 ns at LLC1 = 27 MHz.
Rev. A | Page 5 of 16
VDD
= 1.65 V to 2.0 V, operating temperature range, unless
Min
14.8
12.825
0.6
1.3
0.6
0.6
100
5
45:55
−2.7 + T
−1.3 + T
−2.1 + T
−0.9 + T
9
2.2
7
1
LLC1
LLC1
LLC1
LLC1
/4
/4
/4
/4
Typ
27.0
0.6
Max
±50
110
110
400
300
300
55:45 % duty
3.4
2.4
1.1
2.2
ADV7400A
Unit
MHz
ppm
kHz
MHz
kHz
µs
µs
µs
µs
ns
ns
ns
µs
ms
cycle
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns