AD5421_11 AD [Analog Devices], AD5421_11 Datasheet - Page 22

• Manufacturer Part Number: AD5421_11
• Description: 16-Bit, Serial Input, Loop-Powered, 4 mA to 20 mA DAC
• Manufacturer: AD [Analog Devices]

AD5421
HART COMMUNICATIONS
The AD5421 can be interfaced to a Highway Addressable
Remote Transducer (HART) modem to enable HART digital
communications over the 2-wire loop connection. Figure 45
shows how the modem frequency shift keying (FSK) output is
connected to the AD5421.
To achieve a 1 mA p-p FSK current signal on the loop, the voltage
at the C
output from the HART modem, this means that the signal must
be attenuated by a factor of 4.5. The following equation can be
used to calculate the values of the C
From this equation, the ratio of C
ratio of the capacitor values sets the amplitude of the HART
FSK signal on the loop. The absolute values of the capacitors set
the response time of the loop current, as well as the bandwidth
presented to the HART signal connected at the C
bandwidth must pass frequencies from 500 Hz to 10 kHz. The
two capacitors and the internal impedance, R
pass filter. The 3 dB frequency of this high-pass filter should be
less than 500 Hz and can be calculated as follows:
To achieve a 500 Hz high-pass 3 dB frequency cutoff, the com-
bined values of C
correct HART signal amplitude on the current loop, the final
values for the capacitors are C
MODEM
HART_OUT
4
f
HART
5 .
3
HART_IN
dB
IN
=
Figure 45. Connecting a HART Modem to the AD5421
pin must be 111 mV p-p. Assuming a 500 mV p-p
=
C
C
2
SLEW
HART
×
π
C
HART
×
HART
+
R
AD5421
C
C
DAC
IN
and C
REG
SLEW
C
LOOP–
HART
DRIVE
×
IN
COM
200kΩ
(
1
C
SLEW
HART
HART
should be 21 nF. To ensure the
HART
100nF
= 4.7 nF and C
+
HART
C
to C
SLEW
and C
SLEW
)
DAC
SLEW
is 1 to 3.5. This
, form a high-
IN
SLEW
capacitors.
pin. The
= 16.3 nF.
R
V
L
LOOP
Rev. 0 | Page 22 of 32
Output Noise During Silence and Analog Rate of Change
The AD5421 has a direct influence on two important specifi-
cations relating to the HART communications protocol: output
noise during silence and analog rate of change. Figure 23 shows
the measurement of the AD5421 output noise in the HART
extended bandwidth; the noise measurement is 0.2 mV rms,
within the required 2.2 mV rms value.
To meet the analog rate of change specification, the rate of
change of the 4 mA to 20 mA current must be slow enough so
that it does not interfere with the HART digital signaling. This
is determined by forcing a full-scale loop current change
through a 500 Ω load resistor and applying the resulting voltage
signal to the HART digital filter (HCF_TOOL-31). The peak
amplitude of the signal at the filter output must be less than
150 mV. To achieve this, the rate of change of the loop current
must be restricted to less than approximately 1.3 mA/ms.
The output of the AD5421 naturally slews at approximately
880 mA/ms, a rate that is far too great to comply with the
HART specifications. To reduce the slew rate, a capacitor can be
connected from the C
Current Slew Rate Control section. To reduce the slew rate
enough so that the HART specification is met, a capacitor value
in the region of 4.7 μF is required, resulting in a full-scale
transition time of 500 ms. Many applications will regard this
time as too slow, in which case the slew rate will need to be
digitally controlled by writing a sequence of codes to the DAC
register so that the output response follows the desired curve.
Figure 46 shows a digitally controlled full-scale step and the
resulting filter output. In Figure 46, it can be seen that the peak
amplitude of the filter output signal is less than the required
150 mV, and the transition time is approximately 30 ms.
Figure 46. Digitally Controlled Full-Scale Step and Resulting HART Digital
12
10
8
6
4
2
0
–50
–30
IN
pin to COM, as described in the Loop
Filter Output Signal
–10
TIME (ms)
10
30
50
150
100
50
0
–50
–100
–150