DAC8560A BURR-BROWN [Burr-Brown Corporation], DAC8560A Datasheet - Page 20

• Manufacturer Part Number: DAC8560A
• Manufacturer: BURR-BROWN [Burr-Brown Corporation]

DAC8560
SLAS464 – DECEMBER 2006
20
SERIAL INTERFACE
The DAC8560 has a 3-wire serial interface ( SYNC,
SCLK, and D
and Microwire interface standards, as well as most
DSPs. See the Serial Write Operation timing diagram
for an example of a typical write sequence.
The write sequence begins by bringing the SYNC
line LOW. Data from the D
24-bit shift register on each falling edge of SCLK.
The serial clock frequency can be as high as 30MHz,
making the DAC8560 compatible with high-speed
DSPs. On the 24th falling edge of the serial clock,
the last data bit is clocked in and the programmed
function is executed.
At this point, the SYNC line may be kept LOW or
brought HIGH. In either case, it must be brought
HIGH for a minimum of 33ns before the next write
sequence so that a falling edge of SYNC can initiate
the next write sequence. As previously mentioned, it
must be brought HIGH again before the next write
sequence.
INPUT SHIFT REGISTER
The input shift register is 24 bits wide, as shown in
Table
two bits (PD1 and PD0) are control bits that set the
desired mode of operation (normal mode or any one
of three power-down modes) as indicated in
DB23
0
SYNC
CLK
D
IN
4. The first six bits must be '000000'. The next
0
Output/Mode Does Not Update on the 24th Falling Edge
0
Invalid/Interrupted Write Sequence:
IN
) that is compatible with SPI, QSPI,
0
DB23
0
0
IN
PD1 PD0
line is clocked into the
Table 4. DAC8560 Data Input Register Format
DB0
24th Falling Edge
Figure 65. SYNC Interrupt Facility
D15
Submit Documentation Feedback
D14
Table
D13
5.
D12
D11
A more complete description of the various modes is
located in the
16 bits are the data bits, which are transferred to the
DAC register on the 24th falling edge of SCLK under
normal operation (see
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept
LOW for at least 24 falling edges of SCLK and the
DAC is updated on the 24th falling edge. However, if
SYNC is brought HIGH before the 24th falling edge,
it acts as an interrupt to the write sequence. The shift
register is reset, and the write sequence is seen as
invalid. Neither an update of the DAC register
contents, nor a change in the operating mode
occurs, as shown in
POWER-ON RESET
The DAC8560 contains a power-on-reset circuit that
controls the output voltage during power up. On
power up, all registers are filled with zeros and the
output voltage is zero-scale; it remains there until a
valid write sequence is made to the DAC. This
feature is useful in applications where it is important
to know the state of the output of the DAC while it is
in the process of powering up.
D10
Output/Mode Updates on the 24th Falling Edge
D9
DB23
D8
Valid Write Sequence:
Power-Down Modes
D7
Figure
D6
Table
D5
65.
DB0
5).
24th Falling Edge
D4
section. The next
D3
D2
www.ti.com
D1
DB0
D0