EPM3256A ALTERA [Altera Corporation], EPM3256A Datasheet - Page 32
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EPM3256A
Manufacturer Part Number
EPM3256A
Description
Programmable Logic Device Family
Manufacturer
ALTERA [Altera Corporation]
Datasheet
1.EPM3256A.pdf
(42 pages)
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MAX 3000A Programmable Logic Device Family Data Sheet
32
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
f
t
t
t
IN
IO
FIN
PD1
PD2
SU
H
FSU
FH
CO1
CH
CL
ASU
AH
ACO1
ACH
ACL
CPPW
CNT
CNT
ACNT
ACNT
Table 21. EPM3512A External Timing Parameters
Table 22. EPM3512A Internal Timing Parameters (Part 1 of 3)
Symbol
Symbol
Input to non-registered output
I/O input to non-registered
output
Global clock setup time
Global clock hold time
Global clock setup time of fast
input
Global clock hold time of fast
input
Global clock to output delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
Minimum pulse width for clear
and preset
Minimum global clock period
Maximum internal global clock
frequency
Minimum array clock period
Maximum internal array clock
frequency
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
Parameter
Parameter
C1 = 35 pF
C1 = 35 pF
(2)
(2)
C1 = 35 pF
(2)
(2)
C1 = 35 pF
(3)
(2)
(2),
(2)
(2),
Conditions
Conditions
(4)
(4)
Note (1)
(2)
(2)
(2)
116.3
116.3
Min
Min
5.6
0.0
3.0
0.0
1.0
3.0
3.0
2.5
0.2
1.0
3.0
3.0
3.0
-7
-7
Note (1)
Max
Max
Speed Grade
7.5
7.5
4.7
7.8
8.6
8.6
Speed Grade
0.7
0.7
3.1
87.0
87.0
Min
Min
7.6
0.0
3.0
0.0
1.0
4.0
4.0
3.5
0.3
1.0
4.0
4.0
4.0
-10
-10
Altera Corporation
Max
10.0
10.0
10.4
11.5
11.5
Max
6.3
0.9
0.9
3.6
MHz
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns