ATF1504ASL ATMEL [ATMEL Corporation], ATF1504ASL Datasheet
ATF1504ASL
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ATF1504ASL Summary of contents
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... Pull-up Option on JTAG Pins TMS and TDI • Advanced Power Management Features – Edge-controlled Power-down “L” – Individual Macrocell Power Option – Disable ITD on Global Clocks, Inputs and I/O High- performance Complex Programmable Logic Device ATF1504AS ATF1504ASL Rev. 0950N–PLD–07/02 1 ...
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TQFP Top View I/O/TDI 1 I/O 2 I/O 3 GND 4 PD1/I/O 5 I/O 6 TMS/I/O 7 I/O 8 VCC 9 I/O 10 I/O 11 68-lead PLCC Top View I/O 10 VCCIO 11 I/O/TD1 12 I/O 13 I/O 14 ...
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PQFP Top View I/O 3 I/O 4 VCCIO 5 I/O/TDI I I/O 10 I/O 11 I/O 12 GND 13 I/O/PD1 14 I/O 15 I/O 16 I/O/TMS 17 I/O 18 ...
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Description The ATF1504AS is a high-performance, high-density complex programmable logic device (CPLD) that utilizes Atmel’s proven electrically-erasable memory technology. With 64 logic macrocells and inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic ...
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Block Diagram I/O (MC64)/GCLK3 Unused product terms are automatically disabled by the compiler to decrease power consumption. A security fuse, when programmed, protects the contents of the ATF1504AS. Two bytes (16 bits) of User Signature are accessible to the user ...
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Product Terms and Select Each ATF1504AS macrocell has five product terms. Each product term receives as its Mux possible inputs all signals from both the global bus and regional bus. The product term select multiplexer (PTMUX) allocates the five product ...
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Foldback Bus Each macrocell also generates a foldback product term. This signal goes to the regional bus and is available to four macrocells. The foldback is an inverse polarity of one of the macrocell’s product terms. The sixteen foldback terms ...
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Programmable Pin- The ATF1504AS offers the option of programming all input and I/O pins so that pin- keeper circuits can be utilized. When any pin is driven high or low and then subse- keeper Option for quently left floating, it ...
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All pin transitions are ignored until the PD pin is brought low. When the power-down fea- ture is enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However, the pin’s macrocell may still be ...
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Programming ATF1504AS devices are in-system programmable (ISP) devices utilizing the 4-pin JTAG protocol. This capability eliminates package handling normally required for programming and facilitates rapid design iterations and field changes. Atmel provides ISP hardware and software to allow programming of ...
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DC and AC Operating Conditions Operating Temperature (Ambient (5V) Power Supply CCINT CCIO V (3.3V) Power Supply CCIO DC Characteristics Symbol Parameter Input or I/O Low I IL Leakage Current Input or I/O High I IH Leakage ...
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Absolute Maximum Ratings* Temperature Under Bias.................................. -40°C to +85°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .........................................-2.0V to +7.0V Voltage on Input Pins with Respect to Ground During Programming.....................................-2.0V to +14.0V Programming Voltage ...
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AC Characteristics (Continued) Symbol Parameter f Maximum Clock Frequency MAX t Input Pad and Buffer Delay IN t I/O Input Pad and Buffer Delay IO t Fast Input Delay FIN t Foldback Term Delay SEXP t Cascade Logic Delay PEXP ...
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AC Characteristics (Continued) Symbol Parameter Output Buffer Enable Delay t (Slow slew rate = OFF; ZX1 V = 5.0V pF) CCIO L Output Buffer Enable Delay t (Slow slew rate = OFF; ZX2 V = 3.3V; C ...
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Output AC Test Loads Note: *Numbers in parenthesis refer to 3.0V operating conditions (preliminary). Power-down Mode The ATF1504AS includes an optional pin-controlled power-down feature. When this mode is enabled, the PD pin acts as the power-down pin. When the PD ...
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JTAG-BST/ISP The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the ATF1504AS. The boundary-scan technique involves the inclusion of a shift-regis- Overview ter stage (contained in a boundary-scan cell) adjacent to each component so that ...
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BSC Configuration for Macrocell OEJ OUTJ 0950N–PLD–07/02 Pin BSC 0 Pin 1 Clock TDI Shift TDO Capture Update DR DR TDI Clock Shift Macrocell BSC ATF1504AS(L) TDO D ...
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PCI Compliance The ATF1504AS also supports the growing need in the industry to support the new Peripheral Component Interconnect (PCI) interface standard in PCI-based designs and specifications. The PCI interface calls for high current drivers, which are much larger than ...
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PCI DC Characteristics Symbol Parameter V Supply Voltage CC V Input High Voltage IH V Input Low Voltage IL I Input High Leakage Current IH I Input Low Leakage Current IL V Output High Voltage OH V Output Low Voltage ...
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ATF1504AS Dedicated Pinouts 44-lead Dedicated Pin TQFP INPUT/OE2/GCLK2 40 INPUT/GCLR 39 INPUT/OE1 38 INPUT/GCLK1 37 I/O /GCLK3 35 I/O/PD (1, I/O/TDI (JTAG) 1 I/O/TMS (JTAG) 7 I/O/TCK (JTAG) 26 I/O/TDO (JTAG) 32 GND 4, 16, 24 ...
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ATF1504AS I/O Pinouts 44- 44- 68- lead lead lead MC PLC PLCC TQFP PLCC – – – PD1 ...
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SUPPLY CURRENT VS. SUPPLY VOLTAGE (T = 25° 125 100 STANDARD 75 50 REDUCED POWER MODE 25 0 4.50 4.75 5.00 V (V) CC SUPPLY CURRENT VS. SUPPLY VOLTAGE LOW-POWER ("L") VERSION (T = 25°C, F ...
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OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE (VOL = 0.5V 25° 4.50 4.75 5.00 SUPPLY VOLTAGE (V) NORMALIZED TPD VS. SUPPLY VOLTAGE (T 1.20 1.10 1.00 0.90 0.80 ...
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NORMALIZED TCO VS.TEMPERATURE (V CC 1.2 1.1 1.0 0.9 0.8 -40.0 0.0 25.0 TEMPERATURE (C) NORMALIZED TSU VS. TEMPERATURE (V = 5.0V) CC 1.2 1.1 1.0 0.9 0.8 -40.0 0.0 25.0 TEMPERATURE (C) ATF1504AS( 5.0V) 75.0 75.0 0950N–PLD–07/02 ...
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ATF1504AS Ordering Information CO1 MAX (ns) (ns) (MHz) 7.5 4.5 166 125 10 5 125 15 8 100 15 8 100 Using “C” Product for Industrial To use commercial product for Industrial temperature ranges, ...
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... ATF1504ASL Ordering Information CO1 MAX (ns) (ns) (MHz 83 Using “C” Product for Industrial To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device (7 ns “C” “I”) and de-rate power by 30%. ...
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Packaging Information 44A – TQFP PIN 1 PIN 1 IDENTIFIER e C 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm ...
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PLCC 1.14(0.045) X 45˚ 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. ...
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PLCC 1.14(0.045) X 45˚ 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AE. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. ...
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PLCC 1.14(0.045) X 45˚ 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AF. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. ...
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PQFP Dimensions in Millimeters and (Inches)* *Controlling dimensions: millimeters JEDEC STANDARD MS-022, GC-1 PIN 1 ID 0.65 (0.0256) BSC 0.40 (0.016) 0.22 (0.009) 0.23 (0.009) 0.11 (0.004) TITLE 2325 Orchard Parkway 100Q1, 100-lead Body, ...
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TQFP PIN 1 PIN 1 IDENTIFIER e C 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. ...
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Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Room 1219 Chinachem ...