EPM2210F100A ALTERA [Altera Corporation], EPM2210F100A Datasheet - Page 76
EPM2210F100A
Manufacturer Part Number
EPM2210F100A
Description
MAX II Device Family
Manufacturer
ALTERA [Altera Corporation]
Datasheet
1.EPM2210F100A.pdf
(86 pages)
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5–18
Table 5–23. EPM240 Global Clock External I/O Timing Parameters
MAX II Device Handbook
t
t
t
t
t
t
t
t
f
Note to
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
Symbol
PD1
PD2
SU
H
CO
CH
CL
CNT
CNT
clock input pin maximum frequency.
Table
Worst case
pin-to-pin
delay through
1 look-up
table (LUT)
Best case pin-
to-pin delay
through
1 LUT
Global clock
setup time
Global clock
hold time
Global clock
to output
delay
Global clock
high time
Global clock
low time
Minimum
global clock
period for
16-bit counter
Maximum
global clock
frequency for
16-bit counter
Parameter
5–23:
Table 5–23
Condition
10 pF
10 pF
10 pF
—
—
—
—
—
—
shows the external I/O timing parameters for EPM240 devices.
Min
166
166
1.7
0.0
2.0
3.3
—
—
—
–3 Speed
Grade
304.0
Max
4.7
3.7
4.3
(1)
—
—
—
—
—
Min
216
216
2.2
0.0
2.0
4.0
—
—
—
–4 Speed
Grade
247.5
Max
6.1
4.8
5.6
—
—
—
—
—
Min
266
266
2.7
0.0
2.0
5.0
—
—
—
–5 Speed
Grade
201.1
Max
7.5
5.9
6.9
—
—
—
—
—
Chapter 5: DC and Switching Characteristics
Min
253
253
2.8
2.0
5.4
—
—
—
0
–6 Speed
Grade
© Novermber 2008 Altera Corporation
184.1
Max
7.9
5.8
7.7
—
—
—
—
—
Timing Model and Specifications
Min
335
335
4.7
2.0
8.1
—
—
—
0
–7 Speed
Grade
123.5
Max
12.0
10.5
7.8
—
—
—
—
—
MHz
Unit
ns
ns
ns
ns
ns
ps
ps
ns
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