ATF1504AS_05 ATMEL [ATMEL Corporation], ATF1504AS_05 Datasheet
ATF1504AS_05
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ATF1504AS_05 Summary of contents
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Features • High-density, High-performance, Electrically-erasable Complex Programmable Logic Device – 64 Macrocells – 5 Product Terms per Macrocell, Expandable per Macrocell – 44, 68, 84, 100 Pins – 7.5 ns Maximum Pin-to-pin Delay – Registered Operation up ...
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TQFP Top View I/O/TDI 1 I/O 2 I/O 3 GND 4 PD1/I/O 5 I/O 6 TMS/I/O 7 I/O 8 VCC 9 I/O 10 I/O 11 68-lead PLCC Top View I/O 10 VCCIO 11 I/O/TD1 12 I/O 13 I/O 14 ...
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PQFP Top View I/O 3 I/O 4 VCCIO 5 I/O/TDI I I/O 10 I/O 11 I/O 12 GND 13 I/O/PD1 14 I/O 15 I/O 16 I/O/TMS 17 I/O 18 ...
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Description ATF1504AS(L) 4 The ATF1504AS is a high-performance, high-density complex programmable logic device (CPLD) that utilizes Atmel’s proven electrically-erasable memory technology. With 64 logic macrocells and inputs, it easily integrates logic from several TTL, SSI, MSI, LSI ...
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Block Diagram I/O (MC64)/GCLK3 0950O–PLD–7/05 Unused product terms are automatically disabled by the compiler to decrease power consumption. A security fuse, when programmed, protects the contents of the ATF1504AS. Two bytes (16 bits) of User Signature are accessible to the ...
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Product Terms and Select Mux OR/XOR/CASCADE Logic Flip-flop Output Select and Enable Global Bus/Switch Matrix ATF1504AS(L) 6 Each ATF1504AS macrocell has five product terms. Each product term receives as its possible inputs all signals from both the global bus and ...
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Foldback Bus Figure 1. ATF1504AS Macrocell 0950O–PLD–7/05 Each macrocell also generates a foldback product term. This signal goes to the regional bus and is available to four macrocells. The foldback is an inverse polarity of one of the macrocell’s product ...
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Programmable Pin- keeper Option for Inputs and I/Os Input Diagram Speed/Power Management I/O Diagram ATF1504AS(L) 8 The ATF1504AS offers the option of programming all input and I/O pins so that pin- keeper circuits can be utilized. When any pin is ...
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Design Software Support Power-up Reset Security Fuse Usage 0950O–PLD–7/05 All pin transitions are ignored until the PD pin is brought low. When the power-down fea- ture is enabled, the PD1 or PD2 pin cannot be used as a logic input ...
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Programming ISP Programming Protection ATF1504AS(L) 10 ATF1504AS devices are in-system programmable (ISP) devices utilizing the 4-pin JTAG protocol. This capability eliminates package handling normally required for programming and facilitates rapid design iterations and field changes. Atmel provides ISP hardware and ...
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DC and AC Operating Conditions Operating Temperature (Ambient (5V) Power Supply CCINT CCIO V (3.3V) Power Supply CCIO DC Characteristics Symbol Parameter Input or I/O Low I IL Leakage Current Input or I/O High I IH Leakage ...
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Absolute Maximum Ratings* Temperature Under Bias.................................. -40°C to +85°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .........................................-2.0V to +7.0V Voltage on Input Pins with Respect to Ground During Programming.....................................-2.0V to +14.0V Programming Voltage ...
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AC Characteristics (Continued) Symbol Parameter f Maximum Clock Frequency MAX t Input Pad and Buffer Delay IN t I/O Input Pad and Buffer Delay IO t Fast Input Delay FIN t Foldback Term Delay SEXP t Cascade Logic Delay PEXP ...
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AC Characteristics (Continued) Symbol Parameter Output Buffer Enable Delay t (Slow slew rate = OFF; ZX1 V = 5.0V pF) CCIO L Output Buffer Enable Delay t (Slow slew rate = OFF; ZX2 V = 3.3V; C ...
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Output AC Test Loads Note: *Numbers in parenthesis refer to 3.0V operating conditions (preliminary). Power-down Mode Power Down AC Characteristics Symbol Parameter t Valid I, I/O before PD High IVDH (2) t Valid OE before PD High GVDH (2) t ...
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JTAG-BST/ISP Overview JTAG Boundary-scan Cell (BSC) Testing BSC Configuration for Input and I/O Pins (Except JTAG TAP Pins) Note: The ATF1504AS has pull-up option on TMS and TDI pins. This feature is selected as a design option. ATF1504AS(L) 16 The ...
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BSC Configuration for Macrocell 0950O–PLD–7/05 Pin BSC 0 Pin 1 TDI Shift TDO OEJ OUTJ Capture Update DR DR TDI Clock Shift Macrocell BSC ATF1504AS(L) TDO D Q ...
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PCI Compliance PCI Voltage-to-current Curves for +5V Signaling in Pull-up Mode PCI Voltage-to-current Curves for +5V Signaling in Pull-down Mode ATF1504AS(L) 18 The ATF1504AS also supports the growing need in the industry to support the new Peripheral Component Interconnect (PCI) ...
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PCI DC Characteristics Symbol Parameter V Supply Voltage CC V Input High Voltage IH V Input Low Voltage IL I Input High Leakage Current IH I Input Low Leakage Current IL V Output High Voltage OH V Output Low Voltage ...
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ATF1504AS Dedicated Pinouts 44-lead Dedicated Pin TQFP INPUT/OE2/GCLK2 40 INPUT/GCLR 39 INPUT/OE1 38 INPUT/GCLK1 37 I/O /GCLK3 35 I/O/PD (1, I/O/TDI (JTAG) 1 I/O/TMS (JTAG) 7 I/O/TCK (JTAG) 26 I/O/TDO (JTAG) 32 GND 4, 16, 24 ...
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ATF1504AS I/O Pinouts 44- 44- 68- lead lead lead MC PLC PLCC TQFP PLCC – – – PD1 ...
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SUPPLY CURRENT VS. SUPPLY VOLTAGE (T = 25° 125 100 STANDARD 4.50 4.75 5.00 V (V) CC SUPPLY CURRENT VS. SUPPLY VOLTAGE LOW-POWER ("L") VERSION (T = 25° ...
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OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE (VOL = 0.5V 4.50 4.75 5.00 SUPPLY VOLTAGE (V) NORMALIZED TPD VS. SUPPLY VOLTAGE (T 1.20 1.10 1.00 0.90 0.80 4.5 4.8 ...
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NORMALIZED TCO VS.TEMPERATURE (V CC 1.2 1.1 1.0 0.9 0.8 -40.0 0.0 TEMPERATURE (C) NORMALIZED TSU VS. TEMPERATURE (V CC 1.2 1.1 1.0 0.9 0.8 -40.0 0.0 TEMPERATURE (C) ATF1504AS( 5.0V) 25.0 75.0 = 5.0V) 25.0 75.0 0950O–PLD–7/05 ...
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Ordering Information ATF1504AS Standard Package Options CO1 MAX (ns) (ns) (MHz) 7.5 4.5 166 125 10 5 125 15 8 100 15 8 100 Notes: 1. The last time buy date is Sept. 30, ...
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ATF1504AS Green Package Options (Pb/Halide-free/RoHS Compliant CO1 MAX (ns) (ns) (MHz) 7.5 4.5 166 125 44A 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC) 68J 68-lead, Plastic ...
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ATF1504ASL Standard Package Options CO1 MAX (ns) (ns) (MHz 83 Note: 1. The last time buy date is Sept. 30, 2005 for shaded parts. Using “C” Product for Industrial To use ...
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Packaging Information 44A – TQFP PIN 1 PIN 1 IDENTIFIER e C 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm ...
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PLCC 1.14(0.045) X 45˚ 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. ...
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PLCC 1.14(0.045) X 45˚ 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AE. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. ...
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PLCC 1.14(0.045) X 45˚ 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AF. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. ...
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PQFP PIN 1 ID PIN 0º~7º C 2325 Orchard Parkway San Jose, CA 95131 R ATF1504AS( TITLE 100Q1, 100-lead Body, 3.2 mm Footprint, ...
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TQFP PIN 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and ...
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Revision History ATF1504AS(L) 34 Revision Comments Green package options added. 0950O 0950O–PLD–7/05 ...
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Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 ...