XCR3384XL-10PQG208C XILINX [Xilinx, Inc], XCR3384XL-10PQG208C Datasheet

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XCR3384XL-10PQG208C

Manufacturer Part Number
XCR3384XL-10PQG208C
Description
384 Macrocell CPLD
Manufacturer
XILINX [Xilinx, Inc]
Datasheet

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Part Number:
XCR3384XL-10PQG208C
Manufacturer:
XilinxInc
Quantity:
3 000
Part Number:
XCR3384XL-10PQG208C
Manufacturer:
XILINX
0
DS024 (v2.0) March 31, 2006
Features
Table 1: Typical I
DS024 (v2.0) March 31, 2006
Product Specification
Frequency (MHz)
Low power 3.3V 384 macrocell CPLD
7.0 ns pin-to-pin logic delays
System frequencies up to 135 MHz
384 macrocells with 9,000 usable gates
Available in small footprint packages
-
-
-
-
Optimized for 3.3V systems
-
-
-
-
-
-
Advanced system features
-
-
-
-
-
-
-
-
Fast ISP programming times
Port Enable pin for additional I/O
2.7V to 3.6V supply voltage at industrial grade voltage
range
Programmable slew rate control per output
Security bit prevents unauthorized access
Refer to CoolRunner™ XPLA3 family data sheet
(DS012) for architecture description
Typical I
© 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
144-pin TQFP (118 user I/O)
208-pin PQFP (172 user I/O)
256-ball FBGA (212 user I/O)
324-ball FBGA (220 user I/O)
Ultra low power operation
Typical Standby Current of 18 μA at 25° C
5V tolerant I/O pins with 3.3V core supply
Advanced 0.35 micron five layer metal EEPROM
process
Fast Zero Power™ (FZP) CMOS design
technology
3.3V PCI electrical specification compatible outputs
(no internal clamp diode on any input or I/O)
In-system programming
Input registers
Predictable timing model
Up to 23 clocks available per function block
Excellent pin retention during design changes
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Four global clocks
Eight product term control terms per function block
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
CC
(mA)
CC
vs. Frequency at V
0.018
0
R
2.2
1
CC
= 3.3V, 25°C
24.4
10
0
0
www.xilinx.com
42.4
20
14
XCR3384XL: 384 Macrocell CPLD
Product Specification
Description
The CoolRunner™ XPLA3 XCR3384XL device is a 3.3V,
384 macrocell CPLD targeted at power sensitive designs
that require leading edge programmable logic solutions. A
total of 24 function blocks provide 9,000 usable gates.
Pin-to-pin propagation delays are as fast as 7.0 ns with a
maximum system frequency of 135 MHz.
TotalCMOS Design Technique for Fast
Zero Power
CoolRunner XPLA3 CPLDs offer a TotalCMOS™ solution,
both in process technology and design technique. These
CPLDs employ a cascade of CMOS gates to implement
their sum of products, instead of the traditional sense amp
approach. This CMOS gate implementation allows Xilinx to
offer CPLDs that are both high performance and low power,
breaking the paradigm that to have low power, you must
have low performance. Refer to
ing the I
CPLD (data taken with 24 resetable up/down, 16-bit
counters at 3.3V, 25°C).
Figure 1: Typical I
82.6
40
160
120
280
240
200
80
40
0
CC
0
vs. Frequency of our XCR3384XL TotalCMOS
123.0
60
20
CC
155.6
40
vs. Frequency at V
80
Frequency (MHz)
60
187.8
Figure 1
100
80
and
227.5
100
CC
120
Table 1
= 3.3V, 25°C
120 140
258.1
140
show-
1

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XCR3384XL-10PQG208C Summary of contents

Page 1

... Product Specification 0 14 Description The CoolRunner™ XPLA3 XCR3384XL device is a 3.3V, 384 macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of 24 function blocks provide 9,000 usable gates. Pin-to-pin propagation delays are as fast as 7.0 ns with a maximum system frequency of 135 MHz ...

Page 2

... XCR3384XL: 384 Macrocell CPLD DC Electrical Characteristics Over Recommended Operating Conditions Symbol Parameter (2) V Output High voltage OH V Output Low voltage OL I Input leakage current IL I I/O High-Z leakage current IH (7) I Standby current CCSB (4,5) I Dynamic current CC (6) C Input pin capacitance IN C Clock input capacitance ...

Page 3

... These parameters guaranteed by design and/or characterization, not testing. 5. Typical current draw during configuration 3.6V. 6. Output pF. L DS024 (v2.0) March 31, 2006 Product Specification Parameter (3) (6) DS012 ) for recommended operating conditions. www.xilinx.com XCR3384XL: 384 Macrocell CPLD -7 -10 -12 Min. Max. Min. Max. Min. - 7 ...

Page 4

... XCR3384XL: 384 Macrocell CPLD Internal Timing Parameters Symbol Parameter Buffer Delays T Input buffer delay IN T Fast input buffer delay FIN T Global clock buffer delay GCK T Output buffer delay OUT T Output buffer enable/disable delay EN Internal Register and Combinatorial Delays T Latch transparent delay ...

Page 5

... V Figure 3: AC Load Circuit +3.0V 0V Measurements All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. DS024_04_061802 PD2 www.xilinx.com XCR3384XL: 384 Macrocell CPLD Values 390Ω 390Ω Open Closed Closed Open Closed Closed , ...

Page 6

... XCR3384XL: 384 Macrocell CPLD Pin Descriptions Table 2: XCR3384XL User I/O Pins (1) TQ144 PQ208 Total User 118 172 I/O Pins Notes: 1. XCR3384XL TQ144 JTAG pins are not compatible with other members of the CoolRunner XPLA3 family in the TQ144 package. Table 3: XCR3384XL I/O Pins Function Macro- (1) Block cell TQ144 PQ208 1 ...

Page 7

... R Table 3: XCR3384XL I/O Pins (Continued) Function Macro- (1) Block cell TQ144 PQ208 ...

Page 8

... Table 3: XCR3384XL I/O Pins (Continued) Function Macro- FT256 FG324 Block A14 A19 13 E11 D17 13 A13 A18 13 D12 C17 13 B13 B17 ...

Page 9

... R Table 3: XCR3384XL I/O Pins (Continued) Function Macro- (1) Block cell TQ144 PQ208 147 148 149 150 151 ...

Page 10

... AA3 (2) (2) ( Notes: 1. XCR3384XL TQ144 JTAG pins are not compatible with other - - members of the CoolRunner XPLA3 family in the TQ144 - - package. 2. JTAG pins AA2 ...

Page 11

... Connects Notes: 1. XCR3384XL TQ144 JTAG pins are not compatible with other members of the CoolRunner XPLA3 family in the TQ144 package. 2. Port Enable is brought High to enable JTAG pins when JTAG pins are used as I/O. See family data sheet ( explanation. DS024 (v2.0) March 31, 2006 ...

Page 12

... Device Ordering and (pin-to-pin Part Marking Number delay) XCR3384XL-7TQ144C 7.5 ns XCR3384XL-7TQG144C 7.5 ns XCR3384XL-7PQ208C 7.5 ns XCR3384XL-7PQG208C 7.5 ns XCR3384XL-7FT256C 7.5 ns XCR3384XL-7FG324C 7.5 ns XCR3384XL-10TQ144C 10 ns XCR3384XL-10TQG144C 10 ns XCR3384XL-10PQ208C 10 ns XCR3384XL-10PQG208C 10 ns XCR3384XL-10FT256C 10 ns XCR3384XL-10FG324C 10 ns XCR3384XL-10TQ144I 10 ns XCR3384XL-10TQG144I 10 ns XCR3384XL-10PQ208I 10 ns XCR3384XL-10PQG208I 10 ns XCR3384XL-10FT256I 10 ns XCR3384XL-10FG324I 10 ns XCR3384XL-12TQ144C 12 ns XCR3384XL-12TQG144C 12 ns ...

Page 13

... Updated T spec to correct a typo. Updated AC Load Circuit diagram to HI and Typical and T specifications. Removed T CCSB APRPW www.xilinx.com XCR3384XL: 384 Macrocell CPLD Package Type spec. Added 324-ball Fineline BGA pinouts SU1 INIT delay measurement. POD (added T PCO specification. SOL Operating ...

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