ADSP-2191 AD [Analog Devices], ADSP-2191 Datasheet - Page 32

• Manufacturer Part Number: ADSP-2191
• Description: DSP Microcomputer
• Manufacturer: AD [Analog Devices]

ADSP-2191M
Host Port ACC Mode Read Cycle Timing
Table 18
Ready, ALE, and ACC mode selection, see the Host port modes description
Table 18. Host Port ACC Mode Read Cycle Timing
1
2
t
Measurement is for the second, third, or fourth byte of a host read transaction. The quantity of bytes to complete a host read transaction is dependent on
Parameter
Switching Characteristics
t
t
t
t
t
t
t
t
t
Timing Requirements
t
t
t
t
t
t
t
t
t
t
t
t
NH
the same time.
the data bus size (8 or 16 bits) and the data type (16 or 24 bits).
RHKS1
RHKS2
RHKH
RHS
RHH
RDH
WSHKS
WHHKH
RDD
CSAL
ALCS
RCSW
ALW
ALER
CSR
RCS
WAL
HKRD
ADW
WAD
HKWAL
are peripheral bus latencies (n t
and
Figure 17
HRD Asserted to HACK Asserted (ACK Mode) First Byte
HRD Asserted to HACK Asserted (Setup, ACK Mode)
HRD Deasserted to HACK Deasserted (Hold, ACK Mode)
HRD Asserted to HACK Asserted (Setup, Ready Mode)
HRD Asserted to HACK Deasserted (Hold, Ready Mode)
First Byte
HRD Deasserted to Data Invalid (Hold)
HWR Asserted to HACK Asserted (Setup) During Address
Latch
HWR Deasserted to HACK Deasserted (Hold) During
Address Latch
HRD Deasserted to Data Disable
HCMS or HCIOMS Asserted to HALE Asserted (Delay)
HALE Deasserted to Optional HCMS or HCIOMS
Deasserted
HRD Deasserted to HCMS or HCIOMS Deasserted
HALE Asserted to HWR Asserted
HALE Deasserted to HWR Asserted
HCMS or HCIOMS Asserted to HRD Asserted
HRD Deasserted (After Last Byte) to HCMS or
HCIOMS Deasserted (Ready for Next Read)
HWR Deasserted to HALE Deasserted (Delay)
HACK Asserted to HRD Deasserted (Hold, ACK Mode)
Address Valid to HWR Deasserted (Setup)
HWR Deasserted to Address Invalid (Hold)
HACK Asserted to HWR Deasserted (Hold) During Address
Latch
2
describe Host port read operations in Address Cycle Control (ACC) mode. For more information on ACK,
HCLK
); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at
–32–
on page
2
8.
Min
12t
12t
1
0
1
0
0.5
1
0
0
2.5
1.5
2
1
2
HCLK
HCLK
Max
15t
10
10
10
15t
10
10
10
HCLK
HCLK
+t
+t
NH
NH
1
1
REV. 0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns