ADMCF326 AD [Analog Devices], ADMCF326 Datasheet - Page 20

• Manufacturer Part Number: ADMCF326
• Description: 28-Lead Flash Memory DSP Motor Controller
• Manufacturer: AD [Analog Devices]

ADMCF326
By default following a reset, Bit 8 of the MODECTRL register
is cleared, thus enabling offset mode. In addition, the registers
AUXTM0 and AUXTM1 default to 0xFF, corresponding to
the minimum switching frequency and zero offset. The on-time
registers AUXCH0 and AUXCH1 default to 0x00.
Auxiliary PWM Interface, Registers and Pins
The registers of the auxiliary PWM system are summarized at
the end of the data sheet.
PWM DAC Equation
The auxiliary PWM output can be filtered in order to produce a
low frequency analog signal between 0 V to V
2-pole filter with a 1.2 kHz cutoff frequency will sufficiently
attenuate the PWM carrier. Figure 17 shows how the filter would
be applied.
WATCHDOG TIMER
The ADMCF326 incorporates a watchdog timer that can per-
form a full reset of the DSP and motor control peripherals in the
event of software error. The watchdog timer is enabled by writing a
timeout value to the 16-bit WDTIMER register. The timeout
value represents the number of CLKIN cycles required for the
watchdog timer to count down to zero. When the watchdog timer
reaches zero, a full DSP core and motor control peripheral reset
is performed. In addition, Bit 1 of the SYSSTAT register is set
so that after a watchdog reset, the ADMCF326 can determine
that the reset was due to the timeout of the watchdog timer
and not an external reset. Following a watchdog reset, Bit 1 of
AUX0
AUX1
AUX0
AUX1
2
(AUXTM1 + 1)
AUXPWM
2
2
AUXCH0
AUXCH0
2
R1
AUXCH1
2
2
AUXCH1
(AUXTM0 + 1)
C1
2
R2
2
(AUXTM0 + 1)
(AUXTM0 + 1)
C2
2
R1 = R2 = 13k
C1 = C2 = 10nF
(AUXTM1 + 1)
2
DD
AUXCH1
. For example, a
the SYSSTAT register may be cleared by writing zero to the
WDTIMER register. This clears the status bit but does not
enable the watchdog timer.
On reset, the watchdog timer is disabled and is only enabled
when the first timeout value is written to the WDTIMER register.
To prevent the watchdog timer from timing out, the user must
write to the WDTIMER register at regular intervals (shorter than
the programmed WDTIMER period value). On all but the first
write to WDTIMER, the particular value written to the register
is unimportant since writing to WDTIMER simply reloads the
first value written to this register.
PROGRAMMABLE DIGITAL INPUT/OUTPUT
The ADMCF326 has nine programmable digital input/output
(PIO) pins that are all multiplexed with other functions. The nine
PIO lines PIO0–PIO8 are multiplexed with the serial port (Pins
PIO0/TFS1 to PIO5/RFS1), the CLKOUT (pin PIO6/CLKOUT)
and the auxiliary PWM outputs (Pins PIO7/AUX1 and PIO8/
AUX0). When configured as a PIO, each of these nine pins can
act as an input, output, or an interrupt source.
The operating mode of pins PIO0/TFS1 to PIO7/AUX1 is con-
trolled by the PIOSELECT register. This 8-bit register has a bit
for each input so that the mode of each pin may be selected indi-
vidually. Bit 0 of PIOSELECT controls the operation of the
PIO0/TFS1 pin. Bit 1 controls the PIO1/DT1 pin, etc. Setting
the appropriate bit in the PIOSELECT register causes the cor-
responding pin to be configured for PIO functionality. Clearing
the bit selects the alternate (SPORT, CLKOUT, or AUXPWM)
mode of the corresponding pin. Following power-on reset, all
bits of PIOSELECT are set such that PIO functionality is
selected. The operating mode of the PIO8/AUX0 pin is selected
by Bit 1 of the PIODATA1 register. In a manner identical to the
PIOSELECT register, setting this bit enables PIO functionality
(PIO8) while clearing the bit enables auxiliary PWM functional-
ity (AUX0).
Once PIO functionality has been selected for any or all of these
nine pins, the direction may be set by the 8-bit PIODIR0 regis-
ter (for PIO0 to PIO7) and the 1-bit PIODIR1 register (for PIO8).
Clearing any bit configures the corresponding PIO line as an
input while setting the bit configures it as an output. By default,
following a reset, all bits of PIODIR0 and PIODIR1 are cleared
configuring the PIO lines as inputs.
The data of the PIO0 to PIO8 lines is controlled by the
PIODATA0 register (for PIO0 to PIO7) and Bit 0 of the
PIODATA1 register (for PIO8). These registers can be used to
read data from those PIO lines configured as inputs and write data
to those configured as outputs. Any of the nine pins that have been
configured for PIO functionality can be made to act as an interrupt
source by setting the appropriate bit of the PIOINTEN0 register
(for PIO0 to PIO7) or the PIOINTEN1 register (for PIO8). In
order to act as an interrupt source the pin must also be configured
as an input. An interrupt is generated upon a change of state
(low-to-high transition or high-to-low transition) on any input
that has been configured as an interrupt source. Following a
change of state event on any such input, the corresponding
bit is set in the PIOFLAG0 register (for PIO0 to PIO7) and
PIOFLAG1 (for PIO8) and a common PIO interrupt is gener-
ated. Reading the PIOFLAG0 and PIOFLAG1 registers permits
determining the interrupt source. Reading the PIOFLAG0 and
PIOFLAG1 registers automatically clears all bits of the registers.