EPF10K100E ALTERA [Altera Corporation], EPF10K100E Datasheet - Page 39
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EPF10K100E
Manufacturer Part Number
EPF10K100E
Description
Embedded Programmable Logic Device
Manufacturer
ALTERA [Altera Corporation]
Datasheet
1.EPF10K100E.pdf
(100 pages)
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Altera Corporation
ClockLock & ClockBoost Timing Parameters
For the ClockLock and ClockBoost circuitry to function properly, the
incoming clock must meet certain requirements. If these specifications are
not met, the circuitry may not lock onto the incoming clock, which
generates an erroneous clock within the device. The clock generated by
the ClockLock and ClockBoost circuitry must also meet certain
specifications. If the incoming clock meets these requirements during
configuration, the ClockLock and ClockBoost circuitry will lock onto the
clock during configuration. The circuit will be ready for use immediately
after configuration.
specifications.
Figure 19. Specifications for Incoming & Generated Clocks
The t
nominal output clock period.
ClockLock-
Generated
Clock
I
parameter refers to the nominal input clock period; the t
Input
Clock
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
t
R
t
OUTDUTY
t
Figure 19
CLK1
t
F
t
INDUTY
shows the incoming and generated clock
t
O
t
I
t
t
I
O +
t
INCLKSTB
t
JITTER
t
O –
t
JITTER
O
parameter refers to the
t
I
f
CLKDEV
39