XC2S100E-6FG676C XILINX [Xilinx, Inc], XC2S100E-6FG676C Datasheet - Page 38
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XC2S100E-6FG676C
Manufacturer Part Number
XC2S100E-6FG676C
Description
Spartan-IIE FPGA
Manufacturer
XILINX [Xilinx, Inc]
Datasheet
1.XC2S100E-6FG676C.pdf
(108 pages)
- Current page: 38 of 108
- Download datasheet (5Mb)
Spartan-IIE FPGA Family: DC and Switching Characteristics
IOB Input Delay Adjustments for Different Standards
Input delays associated with the pad are specified for LVTTL. For other standards, adjust the delays by the values shown. A
delay adjusted in this way constitutes a worst-case limit.
38
Data Input Delay Adjustments
T
T
T
T
ILVCMOS18
T
Symbol
ILVCMOS2
T
T
T
T
T
T
IPCI33_3
IPCI66_3
ILVPECL
T
T
T
ISSTL2
ISSTL3
ILVTTL
ILVDS
IGTLP
IHSTL
IAGP
IGTL
ICTT
Standard-specific data input delay
adjustments
Description
www.xilinx.com
LVTTL
LVCMOS2
LVCMOS18
LVDS
LVPECL
PCI, 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
GTL
GTL+
HSTL
SSTL2
SSTL3
CTT
AGP
Standard
–0.11
0.20
0.15
0.15
0.08
0.14
0.14
0.04
0.04
0.04
0.10
0.04
-7
0
0
Speed Grade
DS077-3 (v2.3) June 18, 2008
–0.11
0.20
0.15
0.15
0.08
0.14
0.14
0.04
0.04
0.04
0.10
0.04
Product Specification
-6
0
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R
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