XCV100-6BG256I XILINX [Xilinx, Inc], XCV100-6BG256I Datasheet

XCV100-6BG256I

Manufacturer Part Number

XCV100-6BG256I

Description

Field Programmable Gate Arrays

Manufacturer

XILINX [Xilinx, Inc]

Datasheet

1.XCV100-6BG256I.pdf (4 pages)

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DS003-1 (v2.5 ) April 2, 2001

Features

•

Table 1: Virtex Field-Programmable Gate Array Family Members

DS003-1 (v2.5 ) April 2, 2001

Product Specification

XCV1000

XCV100

XCV150

XCV200

XCV300

XCV400

XCV600

XCV800

Device

XCV50

Fast, high-density Field-Programmable Gate Arrays

Multi-standard SelectIO™ interfaces

Built-in clock-management circuitry

Hierarchical memory system

Flexible architecture that balances speed and density

Densities from 50k to 1M system gates

System performance up to 200 MHz

66-MHz PCI Compliant

Hot-swappable for Compact PCI

16 high-performance interface standards

Connects directly to ZBTRAM devices

Four dedicated delay-locked loops (DLLs) for

advanced clock control

Four primary low-skew global clock distribution

nets, plus 24 secondary local clock nets

LUTs configurable as 16-bit RAM, 32-bit RAM,

16-bit dual-ported RAM, or 16-bit Shift Register

Configurable synchronous dual-ported 4k-bit

RAMs

Fast interfaces to external high-performance RAMs

Dedicated carry logic for high-speed arithmetic

Dedicated multiplier support

Cascade chain for wide-input functions

Abundant registers/latches with clock enable, and

dual synchronous/asynchronous set and reset

Internal 3-state bussing

IEEE 1149.1 boundary-scan logic

Die-temperature sensor diode

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

System Gates

1,124,022

108,904

164,674

236,666

322,970

468,252

661,111

888,439

57,906

CLB Array

16x24

20x30

24x36

28x42

32x48

40x60

48x72

56x84

64x96

Logic Cells

10,800

15,552

21,168

27,648

1,728

2,700

3,888

5,292

6,912

www.xilinx.com

1-800-255-7778

Virtex™ 2.5 V

Field Programmable Gate Arrays

Product Specification

•

Description

The Virtex FPGA family delivers high-performance,

high-capacity programmable logic solutions. Dramatic

increases in silicon efficiency result from optimizing the new

architecture for place-and-route efficiency and exploiting an

aggressive 5-layer-metal 0.22

advances make Virtex FPGAs powerful and flexible alterna-

tives to mask-programmed gate arrays. The Virtex family

comprises the nine members shown in

Building on experience gained from previous generations of

FPGAs, the Virtex family represents a revolutionary step

forward in programmable logic design. Combining a wide

variety of programmable system features, a rich hierarchy of

fast, flexible interconnect resources, and advanced process

technology, the Virtex family delivers a high-speed and

high-capacity programmable logic solution that enhances

design flexibility while reducing time-to-market.

Available I/O

Maximum

Supported by FPGA Foundation™ and Alliance

Development Systems

SRAM-based in-system configuration

0.22

100% factory tested

180

260

284

316

404

512

Complete support for Unified Libraries, Relationally

Placed Macros, and Design Manager

Wide selection of PC and workstation platforms

Unlimited re-programmability

Four programming modes

m 5-layer metal process

Block RAM

114,688

131,072

32,768

40,960

49,152

57,344

65,536

81,920

98,304

Bits

m CMOS process. These

SelectRAM+™ Bits

Table

Maximum

153,600

221,184

301,056

393,216

24,576

38,400

55,296

75,264

98,304

Module 1 of 4

Related parts for XCV100-6BG256I

XCV100-6BG256I Summary of contents

Page 1

... XCV800 888,439 XCV1000 1,124,022 © 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. ...

Page 2

Virtex™ 2.5 V Field Programmable Gate Arrays Virtex Architecture Virtex devices feature a flexible, regular architecture that comprises an array of configurable logic blocks (CLBs) sur- rounded by programmable input/output blocks (IOBs), all interconnected by a rich hierarchy of fast, ...

Page 3

... Virtex™ 2.5 V Field Programmable Gate Arrays XCV400 XCV600 XCV800 166 166 166 316 316 316 404 404 404 404 444 444 512 512 ° ° + ° ° = – +100 C) J XCV1000 404 512 Module ...

Page 4

Virtex™ 2.5 V Field Programmable Gate Arrays Revision History Date Version 11/98 1.0 Initial Xilinx release. 01/99 1.2 Updated package drawings and specs. 02/99 1.3 Update of package drawings, updated specifications. 05/99 1.4 Addition of package drawings and specifications. 05/99 ...

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