CY8C20180_09 CYPRESS [Cypress Semiconductor], CY8C20180_09 Datasheet - Page 4

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CY8C20180_09

Manufacturer Part Number
CY8C20180_09
Description
CapSense Express-8 Configurable IOs
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
Table 2. Pin Definitions - 16 Pin SOIC
Document Number: 001-17346 Rev. *F
Pin Number
10
12
13
14
15
16
11
1
2
3
4
5
6
7
8
9
I
I
GP0[3]
GP0[4]
GP0[0]
GP0[1]
2
2
GP1[0]
GP1[1]
GP1[2]
GP1[3]
GP1[4]
GP0[2]
Name
XRES
CSInt
C SDA
C SCL
VSS
V
DD
I2CSDA
I2CSCL
[1]
GP0[4]
GP0[3]
GP0[0]
GP0[1]
GP1[0]
CSInt
Figure 2. Pin Diagram - 16 Pin SOIC
1
4
8
2
3
6
7
5
Configurable as CapSense or GPIO
Integrating Input.The external capacitance is required only if 5:1 SNR cannot
be achieved. Typical range is 10 nF to 100 nF
Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
I
I
Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
Ground connection
Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
Active HIGH external reset with internal pull down
Configurable as CapSense or GPIO
Supply voltage
2
2
C clock
C data
(Top View)
SOIC
16
15
13
11
10
14
12
9
GP0[2]
XRES
GP1[4]
GP1[3]
V
V
GP1[2]
GP1[1]
Description
SS
DD
CY8C20180
Page 4 of 16
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