ATAM510X-ILQY ATMEL [ATMEL Corporation], ATAM510X-ILQY Datasheet - Page 43
ATAM510X-ILQY
Manufacturer Part Number
ATAM510X-ILQY
Description
MARC4 4-bit MTP Universal Microcontroller
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.ATAM510X-ILQY.pdf
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3.5.3.3
4711B–4BMCU–01/05
Timer 0 Control Register (T0CR)
Table 3-14.
The interrupt flags will be set whenever the associated condition occurs irrespective of whether
the corresponding interrupt is triggered. Therefore, the status flags are still set if the interrupt
condition occurs when the interrupt is masked. To see exactly when the flags are set, see T0MO
control code,
Reading from the timer/counter auxiliary register will access the Timer 0 Interrupt Status Regis-
ter (T0SR).
The T0CR is responsible for the predivision of the selected Timer 0 input clock (see TCCR). It
can be divided or used directly as a clock for the up/down counter. Bit 0 is the mask bit for Timer
0 interrupt.
Table 3-15.
T0FS3 ... 1
T0IM
3 2 1 0
0 0 0 x
0 0 1 x
0 1 0 x
0 1 1 x
1 0 0 x
1 0 1 x
1 1 0 x
1 1 1 x
x x x 1
x x x 0
Code
T0CR
3 2 1 0
x x x 1
x x 1 x
x 1 x x
Code
Table 3-13 on page
Function
Timer 0 interrupt disabled
Timer 0 interrupt enabled
Timer 0 prescaler divide by 256
Timer 0 prescaler divide by 128
Timer 0 prescaler divide by 64
Timer 0 prescaler divide by 32
Timer 0 prescaler divide by 16
Timer 0 prescaler divide by 8
Timer 0 prescaler divide by 4
Timer 0 prescaler bypassed
Timer 0 Interrupt Status Register (T0SR)
Timer 0 Control Register (T0CR)
– Timer 0 Interrupt Mask
– Timer 0 prescaler division factor code
T0FS3
Bit 3
Function
Timer 0 compare has occurred (Timer 0 = T0CP)
Timer 0 overflow or underflow has occurred
Timer 0 measurement completed
T0FS2
Bit 2
Subport address (indirect write access): '1'hex of Port address '9'hex
42.
T0FS1
Bit 1
T0IM
Bit 0
Reset value: 1111b
ATAM510
43
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