STPC4EDBC STMICROELECTRONICS [STMicroelectronics], STPC4EDBC Datasheet - Page 39

• Manufacturer Part Number: STPC4EDBC
• Description: X86 Core PC Compatible Information Appliance System-on-Chip
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

4.5.2 RESET SEQUENCE
Figure 4-4
STPC, also called warm reset.
The constraints on the strap options and the bus
activities are the same as for the cold reset.
The SYSRSTI# pulse duration must be long
enough to have all the strap options stabilized and
must be adjusted depending on resistor values.
Figure 4-4. Reset timing diagram
14 M Hz
SYSRSTI#
ISACLK
Strap Options
HCLK
PCI_CLK
SYSRSTO#
describes the reset sequence of the
M D[63:0]
Release 1.5 - January 29, 2002
1.6 V
VALID CONFIGURATION
It is mandatory to have a clean reset pulse without
glitches as the STPC could then sample invalid
strap option setting and enter into an umpredicta-
ble mode.
While SYSRSTI# is active, the PCI clock PLL runs
in open loop mode at a speed of few 100’s KHz.
ELECTRICAL SPECIFICATIONS
2.3 m s
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