CY8C54 CYPRESS [Cypress Semiconductor], CY8C54 Datasheet - Page 10

• Manufacturer Part Number: CY8C54
• Description: Programmable System-on-Chip (PSoC)
• Manufacturer: CYPRESS [Cypress Semiconductor]

Vcca. Output of analog core regulator and input to analog core.
Requires a 1 µF capacitor to Vssa. Regulator output not for
external use.
Vccd. Output of digital core regulator and input to digital core.
Requires a capacitor from each Vccd pin to Vssd; see
System
Vdda. Supply for all analog peripherals and analog core
regulator. Vdda must be the highest voltage present on the
device. All other supply pins must be less than or equal to
Vdda.
Vddd. Supply for all digital peripherals and digital core regulator.
Vddd must be less than or equal to Vdda.
Vssa. Ground for all analog peripherals.
Vssb. Ground connection for boost pump.
Document Number: 001-55036 Rev. *A
SRAM
SRAM
32 KB
32 KB
on page 22. Regulator output not for external use.
Interrupt Inputs
JTAG/SWD
Bus
Matrix
Bus
Matrix
Debug Block
AHB Spokes
(Serial and
Controller
Vectored
Interrupt
Nested
(NVIC)
JTAG)
GPIO &
EMIF
AHB
I- Bus
AHB Bridge & Bus Matrix
Figure 4-1. ARM Cortex-M3 Block Diagram
PRELIMINARY
C-Bus
D-Bus
AHB
Digital
Prog.
Cortex M3 CPU Core
Peripherals
PHUB
AHB
Power
S-Bus
Cortex M3 Wrapper
Analog
Prog.
Vssd. Ground for all digital logic and I/O pins.
Vddio0, Vddio1, Vddio2, Vddio3. Supply for I/O pins. See
pinouts for specific I/O pin to Vddio mapping. Vddio must be less
than or equal to Vdda.
XRES (and configurable XRES). External reset pin. Active low
with internal pullup. In 48-pin SSOP parts, P1[2] is configured as
XRES. In all other parts the pin is configured as a GPIO.
4. CPU
4.1 ARM Cortex-M3 CPU
The CY8C54 family of devices has an ARM Cortex-M3 CPU
core. The Cortex-M3 is a low power 32-bit three-stage pipelined
Harvard architecture CPU that delivers 1.25 DMIPS/MHz. It is
intended for deeply embedded applications that require fast
interrupt handling features.
PSoC
DMA
Bus
Matrix
Functions
Special
®
Watchpoint and
Instrumentation
and Breakpoint
Trace Module
Trace (DWT)
5: CY8C54 Family Data Sheet
Flash Patch
(FPB)
(ITM)
Data
Cache
Trace Module
Interface Unit
Embedded
Trace Port
(TPIU)
(ETM)
256 KB
Flash
ECC
Trace Pins:
5 for TRACEPORT or
1 for SWV mode
Page 10 of 93
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