WL800KG MITEL [Mitel Networks Corporation], WL800KG Datasheet - Page 7

• Manufacturer Part Number: WL800KG
• Description: 2.5GHz Frequency Synthesiser
• Manufacturer: MITEL [Mitel Networks Corporation]

FUNCTIONAL DESCRIPTION
Reference Frequency
crystal in conjunction with an on chip oscillator maintaining
circuit. A buffer circuit provides a low level voltage output
signal at the crystal frequency to drive the logic in the protocol
and control chip. The crystal frequency is divided by 20 to
provide the reference signal to the phase comparator.
Counters / Dividers
An external oscillator is used to feed the input of the
preamplifier in the synthesiser, (this isolates the counters from
the oscillator and reduces the level of drive signal required by
the synthesiser). The output of the preamplifier drives a dual
modulus prescaler with ratios of 48/49, which in turn then
drives the standard A-M counter arrangement. The A counter
then provides the modulus control signal back to the
prescaler. The counter system has an overall division ratio
given by the formula MN+A where N is the lower divide ratio
of the prescaler (48).
to allow the oscillator to be tuned over the required frequency
range of 144 channels at 1MHz spacing. The M count ratio can
be programmed over the range 49 to 52 and the A counter from
1 to 48 giving a total divide ratio from 2353 to 2544 which is
greater than necessary to tune the required frequency range.
Programming
three wire serial data bus consisting of Enable, Clock and Data
signals.
ming sequence and remains low for the duration of the 8 serial
data bits. A positive clock edge is required to strobe each data
bit into the input register. When all 8 data bits are entered, the
enable pin is taken high forcing the counters to zero and
preloading the new count data when the counter is next
clocked . The charge pump is disabled for a short period after
the enable pin goes low to prevent glitch energy being trans-
ferred to the VCO.
The divide ratio of the M and A counters is programmable
The programming data for the synthesiser is entered via a
The enable signal is taken low at the start of the program-
The reference frequency is generated using a 20MHz
Phase Detectors
rating dead band suppression is used in conjunction with a
charge pump to steer the VCO. An internal op-amp maintains
the charge pump pin at the same voltage as the charge pump
reference by virtual earth principles. The op-amp is split into
two parts with the first section having a relatively low current
drive capability but including the high gain stages of the
amplifier. The second stage has a controlled voltage gain of
1/3 but high input impedance and low output impedance. This
minimises loading to the high output impedance of the first
stage and provides sufficient drive current via the loop filter to
maintain virtual earth at the charge pump output. The output
from the first stage is designed to swing close to the positive
and negative rails so as to provide maximum voltage swing to
the varactor controlling the VCO. A compensating capacitor
can be connected to this point to stabilise the amplifier.
indication to the controller that the phase locked loop is locked,
preventing transmission on illegal frequencies.
Antimodulation
The WL800 contains a data buffer circuit which accepts
transmit data from the CMOS controller circuit and converts
the CMOS input to a tristate current output for driving the
transmit spectrum shaping filter. The buffer gives zero current
for a logic “1” input, a high current (+2I) for a logic “0” and a
current midway between the two (+I) for use during the
transmit amplifier power up/down period and during receive.
This function prevents the synthesiser centring its frequency
on either a logic “1” or “0” and removes the possibility of over-
modulation at the start of a transmission. The amplitude of the
output current and therefore modulation index of the radio is
controlled by an external resistor connected to ground.
A data compensation path is included which counteracts the
tendency of the PLL to drift back to centre frequency when the
data is non-white. This is achieved by charging an external
capacitor with a current +I when data is low, and discharging
it by a current -I when data is high. The capacitor voltage,
which then represents an integrated form of the data is
converted to a current via a buffer and an external resistor
(RCOMP), and fed into the Loop Filter in addition to the Phase
Detector output. During Receive Mode, the capacitor is
charged to the Charge Pump Reference voltage.
A conventional digital phase frequency detector incorpo-
A lock detect output (active low) is provided to give an
WL800
7