AT22LV10-L ATMEL [ATMEL Corporation], AT22LV10-L Datasheet - Page 7

• Manufacturer Part Number: AT22LV10-L
• Description: Low-Voltage UV Erasable Programmable Logic Device
• Manufacturer: ATMEL [ATMEL Corporation]

Preload of Registered Outputs
The registers in the AT22LV10 and AT22LV10L are pro-
vided with circuitry to allow loading of each register asyn-
chronously with either a high or a low. This feature will
simplify testing since any state can be forced into the regis-
ters to control test sequencing. A V
will force the register high; a V
dent of the polarity bit (C0) setting. The preload state is
entered by placing an 11.5V to 13V signal on pin 8 on
Power-Up Reset
The registers in the AT22LV10 and AT22LV10L are
designed to reset during power up. At a point delayed
slightly from VCC crossing 2.5V, all registers will be reset
to the low state. The output state will depend on the polarity
of the output buffer.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
uncertainty of how VCC actually rises in the system, the fol-
lowing conditions are required:
1. The V
2. After reset occurs, all input and feedback setup
3. The clock must remain stable during t
Pin Capacitance (f = 1 MHz, T = 25°C)
Note:
Erasure Characteri s tics
The entire fuse array of an AT22LV10 or AT22LV10L is
erased after exposure to ultraviolet light at a wavelength of
2537 Å. Complete erasure is assured after a minimum of
20 minutes exposure using 12,000 W/cm
spaced one inch away from the chip. Minimum erase time
for lamps at other intensity ratings can be calculated from
C
C
IN
OUT
times must be met before driving the clock pin high,
and
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
CC
rise must be monotonis;
IL
will force it low, indepen-
IH
level on the I/O pin
Typ
5
6
PR
2
.
intensity lamps
(1)
Max
DIPs, and pin 10 on SMPs. When the clock pin is pulsed
high, the data on the I/O pins is placed into the ten regis-
ters.
the minimum integrated erasure dose of 15 W
prevent unintentional erasure, an opaque label is recom-
mended to cover the clear window on any UV erasable
PLD which will be subjected to continuous fluorescent
indoor lighting or sunlight.
8
8
Level forced on registered output
pin during preload cycle
t
Parameter
PR
Power-Up
Reset Time
Description
V
V
IH
IL
Units
pF
pF
Min
Conditions
V
V
IN
OUT
Typ
600
Register state after
cycle
High
Low
= 0V
= 0V
Max
1000
•
sec/cm
Units
2
ns
. To
7