XC7336-12 XILINX [Xilinx, Inc], XC7336-12 Datasheet

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XC7336-12

Manufacturer Part Number
XC7336-12
Description
36-Macrocell CMOS EPLD
Manufacturer
XILINX [Xilinx, Inc]
Datasheet

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Part Number
Manufacturer
Quantity
Price
Part Number:
XC7336-12PC44C
Manufacturer:
XILINX
0
Features
• Ultra high-performance EPLD
• New low power XC7336Q
• 100% routable with 100% utilization
• Incorporates four PAL-like 24V9 Fast Function Blocks
• 36 Output Macrocells
• High-performance P compatible
• Peripheral Component Interface (PCI) compatible
• JEDEC standard 3.3 V or 5 V I/O operation
• Multiple security bits for design protection
• 44-pin leaded chip carrier and 44-pin quad flat pack
General Description
The XC7336 is a member of the Xilinx XC7300 EPLD fam-
ily. It consists of four PAL-like 24V9 Fast Function Blocks
Figure 1. XC7336 Functional Block Diagram
– 5 ns pin-to-pin speed on all fast inputs
– 167 MHz maximum clock frequency
– Programmable I/O architecture
– 24 mA drive
packages
PQ44
22
10
21
20
19
18
16
14
13
12
11
1
2
3
5
6
7
8
9
PC44
28
11
12
13
14
15
16
27
26
25
24
22
20
19
18
17
7
8
9
I/FO/FI
I/FO/FI
I/FO/FI
I/FO/FI
I/FI
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
This document was created with FrameMaker 4 0 2
MC1-1
MC1-2
MC1-3
MC1-4
MC1-5
MC1-6
MC1-7
MC1-8
MC1-9
MC4-1
MC4-2
MC4-3
MC4-4
MC4-5
MC4-6
MC4-7
MC4-8
MC4-9
9
9
19
FFB1
FFB4
3
3
9
9
12
12
12
12
12
12
2-23
UIM
34
Product Specifications
XC7336
36-Macrocell CMOS EPLD
interconnected by the 100%-populated Universal Intercon-
nect Matrix (UIM ).
Each Fast Function Block has 24 inputs and contains nine
Macrocells configurable for registered or combinational
logic. The nine Macrocell outputs feed back to the UIM and
can simultaneously drive the output pads.
The UIM allows 100% connectivity between all function
blocks and input pins, providing the ability to utilize 100% of
the device while eliminating routing issues.
The XC7336 is designed in 0.8
ogy, in speed grades ranging from 5 to15 ns. The XC7336Q
is also available now, providing lower power consumption in
-10, -12 and -15 ns speed grades.
Device logic is automatically configured to the user’s speci-
fications using the XEPLD software. The XEPLD software
is capable of optimizing and collapsing logic. The SMART-
switch software/hardware feature allows implementation of
buried combinatorial logic functions in the UIM, thus
increasing device utilization. The XEPLD software supports
third party schematic capture and HDL entry tools, as well
as direct equation-based text files. Using a workstation or
PC platform, designs are automatically mapped into the
XC7336 in a matter of minutes.
12
12
12
12
12
12
9
9
3
3
FFB2
FFB3
MC2-9
MC2-8
MC2-7
MC2-6
MC2-5
MC2-4
MC2-3
MC2-2
MC2-1
MC3-9
MC3-8
MC3-7
MC3-6
MC3-5
MC3-4
MC3-3
MC3-2
MC3-1
15
9
9
I/FO/FI/MR
FO/FCLK0
FO/FCLK1
FO/FOE1
FO/FOE0
I/FO/FI
I/FO/FI
I/FO/FI
I/FO/FI
I/FO/FI
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FO
I/FI
CMOS EPROM technol-
PC44
42
29
30
33
34
35
36
37
38
39
40
43
44
1
2
3
4
5
6
PQ44
X5452
36
23
24
27
28
29
30
31
32
33
34
37
38
39
40
41
42
43
44

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XC7336-12 Summary of contents

Page 1

... The XC7336 is designed in 0.8 ogy, in speed grades ranging from 5 to15 ns. The XC7336Q is also available now, providing lower power consumption in -10, -12 and -15 ns speed grades. Device logic is automatically configured to the user’s speci- fi ...

Page 2

... The Macrocell output can also be routed back as an input to the Fast Function Block, and the UIM. Power-On Characteristics/Master Reset The XC7336 device undergoes a short internal initializa- tion sequence upon device powerup. During this time (t ), the outputs remain 3-stated while the device is SET confi ...

Page 3

... NAND NOR functions. This offers an addi- tional level of logic without additional speed penalty. 3 Interface Configuration The XC7336 can be used in systems with two different supply voltages: 3.3 V and 5 V. Each XC7336 device has separate V connections to the internal logic (V CC ...

Page 4

... Macrocells in high-performance mode Macrocells in low-power mode Total number of Macrocells used f = Clock frequency (MHz) Figure 4 shows a typical power calculation for the XC7336 device, programmed as two 16-bit counters and operating at the indicated clock frequency. 200 150 100 Clock Frequency (MHz) Figure 4 ...

Page 5

Here are just a few of the XEPLD Development System features: • Automatic Optimization and Mapping Designs are automatically minimized and mapped into the devices for optimal efficiency and high performance. Critical logic functions are automatially assigned to special resources ...

Page 6

... XC7336 CMOS EPLD DC Characteristics Over Recommended Operating Conditions Symbol Parameter 5 V TTL High-level output voltage V OH 3.3 V High-level output voltage 5 V TTL Low-level output voltage V OL 3.3 V Low-level output voltage I Input leakage current IL I Output high-Z leakage current OZ C Input capacitance for Input and I/O pins ...

Page 7

... FCLK TEST R 1 Device Output Device Input Rise and Fall Times < 3ns V Level CCIO TEST 5.0 V 160 120 3.3 V 3.3 V 260 360 2-29 XC7336-10 XC7336-12 XC7336-15 Min Max Min Max Min 10.0 12.0 15.0 19.0 5.0 6.0 7.0 10.0 13.0 15 8.0 9.0 10.0 12.0 10.0 12.0 100.0 80.0 66.7 5.0 5.5 6 FOD FOE t WH ...

Page 8

... Max 1.0 1.5 5 2.0 3.5 2.5 1.5 1.0 2.5 1.0 1.0 0.5 0.5 2.0 2.0 0.6 0.8 0.5 4.0 XC7336-5 XC7336-7 Min Max Min Max 1.5 2.5 2.0 3.0 3.5 4.5 1.5 1.5 2-30 t FSUI t FOUT t FCOI t FPDI t FHI t FAOI XC7336-10 XC7336-12 XC7336-15 Min Max Min Max Min Max 1.5 2.0 2.0 5.5 7.0 8.0 2.5 3.0 4.0 2.5 3.0 3.0 1.0 1.0 1.0 0.5 1.0 1.0 2.5 3.0 4.0 1.0 1.2 1.5 5.0 6.5 8.0 XC7336-10 XC7336-12 XC7336-15 Min Max Min Max Min Max 3.5 4.0 5.0 4.5 5.0 7.0 5.0 7.0 8.0 2.5 3.0 4.0 Pin X5221 Units Units ...

Page 9

Combinatorial Switching Characteristics Input, I/O Pin UIM Delay Logic Delay P-Term Assignment Delay Transparent Register Delay Output Buffer Output Pin Asynchronous Clock Switching Characteristics Input, I/O Pin t IN Input, I/O Delay UIM Delay Clock at Register Data from Logic ...

Page 10

... XC7336 CMOS EPLD Synchronous Clock Switching Characteristics F Pin CLK Data/CE at Input I/O Register Input, I/O Register to UIM Fast Clock Input Delay Data at Input I/O Pin Data at Input Register Register to Output Pin PQ44 PC44 Input 39 1 I/FO/ I/FO/ I/FO/ I/FO/ FO/FCLK0 44 6 FO/FCLK1 1 7 I/FO/ I/FO 3 ...

Page 11

... Commercial = 0° to +70° Industrial = -40° to 85°C The Programmable Logic Company SM XC7336 - Temperature Range Speed Number of Pins Package Type Low Power -10, -12, -15 speeds 15 ns pin-to-pin delay 12 ns pin-to-pin delay 10 ns pin-to-pin delay 7 ...

Page 12

... XC7336 CMOS EPLD 2-34 ...

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