AT83C26_07 ATMEL [ATMEL Corporation], AT83C26_07 Datasheet
AT83C26_07
Related parts for AT83C26_07
AT83C26_07 Summary of contents
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Features • 5 Smart Card Interfaces – Compliance with ISO 7816, EMV2000, GIE-CB and GSM Standards – Direct Connection to the Smart Cards Logic Level Shifters Short Circuit Current Limitation 4kV+ ESD Protection (MIL/STD 883 Class 3) – ...
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Acronyms TWI: Two Wire Interface POR: Power On Reset PFD: Power Fail Detect ART: Automatic Reset Transition ATR: Answer To Reset Block Diagram VCC VSS BYPASS Voltage EVCC supervisor POR/PFD RESET INT A2/CK, A1/RST TWI SCL Controller SDA I/O1 I/0 ...
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Pin Description Pinout (Top View) VQFP48 Pinout CRST3/CC82 CIO3/CC42 QFN48 Pinout CRST3/CC82 CIO3/CC42 7511D–SCR–02/ CVCC3 1 2 CCLK3 3 4 CVCC4 5 VQFP 48 6 CRST4 TOP VIEW CCLK4 7 ...
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Signals Table 1. Ports Description VQFP48 or QFN48 Pad Name Pad Internal Pin number Power Supply 1 CVCC3 2 CRST3/CC82 3 CCLK3 4 CIO3/CC42 5 CVCC4 6 CRST4 7 CCLK4 8 CIO4 9 CIO5 10 CCLK5 11 CRST5 12 CVCC5 ...
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Table 1. Ports Description (Continued) VQFP48 or QFN48 Pad Name Pin number 22 LIA 23 CVSS1 24 VCC 25 VSS 26 BYPASS 27 SDA 28 SCL 29 IO2 30 IO1 31 AUX2 32 AUX1 33 A1/RST 34 A2/CK 35 CLK ...
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Table 1. Ports Description (Continued) VQFP48 or QFN48 Pad Name Pad Internal Pin number Power Supply 38 CVSSB 39 LIB 40 CVCCB 41 CVCCB 42 RESET 43 CPRES2 44 CVCCINB 45 CVCC2 46 CRST2 47 CCLK2 48 CIO2 Note: AT83C26 ...
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Pad Type Description To simplify the understanding of Figure 1. to Figure 8., a shortcut is possible by replacing the weak transistor by a 100k Ohms pull-up resistor, the medium transistor by a 10k Ohms pull-up resistor and the strong ...
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Input/Output with Open Drain Configuration (SDA, SCL, RESET) Figure 3. Input/Output with Open Drain Configuration Port latch Data Output Configuration (CCLKn with Figure 4. Output Configuration Port latch Data Output Configuration (CRSTn with ...
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Open drain Output with programmable pull-up Configuration (INT) Figure 6. Open Drain Output with programmable pull-up Input Configuration (A1, A2, CLK, BYPASS) Figure 7. Input Input with programmable pull-up Configuration (CPRES1, CPRES2) Figure 8. Input with programmable pull-up 7511D–SCR–02/07 INT_PULLUP ...
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Operational Modes TWI Bus Control The Atmel Two-Wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds 400 Kbits per second, based on a byte-oriented ...
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Figure 1. Data transfer on TWI bus Address Byte The first byte to send to the device is the address byte. The device controls if the hardware address (A2/CK, A1/RST pins on reset) corresponds to the address given in the ...
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RESET pin The TWI ADDRESS BYTE is sampled on A2/CK and A1/RST after a rising edge on RESET pin. The delay between the rising edge and the sampling of A2/CK and A1/RST is t1. The value for ...
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Table 3. SC2 and SC3 shared IOs Pin name SC2_FULL = 1 SC3 interface not available CPRES2 CPRES2 CRST2 CRST2 CIO2 CIO2 CCLK2 CCLK2 CRST3/CC82 CC82 CIO3/CC42 CC42 CCLK3 unused DCDC Converters The DC/DC A converter is used to provide ...
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Figure 4. Clock Block Diagram with Software Activation CRST controller CRSTn for SCn interface (n=1, 2) The CRSTn output pin is driven by the CARDRSTn bit value or by A1/RST pin. Three modes are available: • If the ARTn bit ...
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CRSTn for SCn interface ( The CRSTn output pin is driven by the CARDRSTn bit value (see SCn_CFG2 register). Two modes are available: • If the ARTn bit is reset, CRSTn pin is driven by CARDRSTn bit. ...
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CIO2, CC42, CC82 controller for SC2 interface Figure 8. CIO2, CC42, CC82 Block Diagram AUX1 AUX2 The SC2_FULL bit must be set to use CC42 and CC82. CIOn controller for SCn interface (n= The CIOn output pin is ...
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Transparent mode arbitration system The first between IO and CIO to force a low level becomes the master. The slave signal is grounded after t1 delay: t1 max = 2* (CLK period). Figure 10. Bidirectional mode The minimum delay for ...
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CCLKn and CIOn (n slew rate control Three registers SLEW_CTRL_1, SLEW_CTRL_2 and SLEW_CTRL_3 control the slew rate of the CIOn and CCLKn signals. Each signal has 2 control bits. An automatic mode is proposed. The VCARDn[1:0] value is ...
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Card Presence Detection Card presence detection for SC1 interface The card presence signal is connected on the CPRES1 pin. The polarity of card presence con- tact is selected with the CARDDET1 bit (see SC1_CFG1 register). A programmable filtering is controlled ...
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DC/DC converters DC/DC A converter The DC/DC A converter is controlled by VCARD1[1:0], SHUTDOWNA, ICCADJA, STEPREGA, VCARD_OK1 and DEMBOOSTA[1:0] bits. The DC/DC A converter cannot be switched on while the CPRES1 pin remains inactive. If CPRES1 pin becomes inactive while ...
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Figure 9. DC/DC A Converter Initialization Procedure DC/DC B converter The DC/DC B converter is controlled by DCDCB register. The DC/DC B converter can be switched on even if CPRES2 pin remains inactive. A write operation in VDCB[1:0] (0x01, 0x02, ...
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The DC/DCB sensitivity to any overflow current can be modified (20%) by using the ICCADJB bit (DC/DCB register). Initialization Procedure for DC/DC B converter The initialization procedure is described in flow chart: • Select the DC/DC B level by means ...
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LDO initialization Procedure When the DC/DC B voltage rises the selected voltage (VDCB_OK=1), the card voltage selection on CVCC2, CVCC3, CVCC4 or CVCC5 starts the corresponding LDO. The CVCC2 card voltage must be started in first (if needed). When the ...
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Activation Sequence Overview (n= The activation sequence on SC1 is only available if a card is detected on CPRES1 (CARDIN1 bit = 1). The activation sequence on SC2 is only available if a card is detected ...
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Figure 14. Software activation without automatic control (ARTn bit = 0) Note: – – Software activation for SCn (n= interfaces and ARTn bit = 1 The following sequence can be applied: 1. Card Voltage is set ...
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CRSTn signal is not set and the CAPTURE_MSB and CAPTURE_LSB registers contain the value of the counter at the arrival of the ATR. If the ATR arrives after the rising edge on CRSTn pin and before the card clock ...
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The CRST signal will be equal to 0 during the number of clock cycles programmed in TIMER_MSB and TIMER_LSB. Then, the CRST signal will Figure 16. Warm reset with ARTn bit = 1 Deactivation Sequence Overview The ...
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Reset pin going low (SC1, SC2, SC3, SC4, SC5) • Power Fail (VPFDP self-timed sequence which cannot be interrupted when started (see Figure 17). Each step is separated by a delay based on Td equal to ...
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Figure 18. Power Fail Detection Figure 19. Emergency deactivation sequence During an emergency deactivation, the signals fall according to the order described in Fig18. Transparent mode Full transparent mode on SCn interfaces (n= the micro controller outputs ISO ...
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Figure 20. Transparent Mode Description Micro controller Full transparent mode on SCn interfaces ( The transparent mode with A2/CK is also available for SC3, SC4 and SC5 interfaces without CC4 and CC8. Figure 21. Transparent Mode Description ...
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Several AT83C26 devices can share the same interrupt pin and the micro controller can identify the interrupt sources by polling the interrupt bits of the AT83C26 devices using TWI commands. A TWI read command of the interrupt bit corresponding to ...
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After the reading and the clear of the interrupt bits, several bits are used to control the status. Table 5. Status bits description Bit name Register name CARDIN1 SC1_STATUS CARDIN2 SC1_STATUS VCARD_OK1 SC1_STATUS VCARD_OK2 SC2_CFG0 VCARD_OK3 SC3_CFG0 VCARD_OK4 SC4_CFG0 VCARD_OK5 ...
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Write Commands The write commands are: 1. General Call Reset: A general call followed by the value 06h has the same effect as a Reset command. 2. Reset: Initialize all the logic and the TWI interface as after a power-up ...
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Write SC5 interface: SC5_CFG0, SC5_CFG2 Configuration of SIM/SAM interface 5. 11. Write DCDCB config: DCDCB, LDO Configuration of DCDCB converter. 12. Write SLEW_CTRL config: SLEW_CTRL_1, SLEW_CTRL_2, SLEW_CTRL_3 Configuration of slew rate for CCLKn and CIOn ( ...
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Read Command After a write command, even with a length of 0 byte, the next read operation is performed on the corresponding byte. The write command sets the “read pointer”. After the reset, the “read pointer” SC1 registers ...
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Registers summary The table below gives a quick view on AT83C26 registers. Table 8. Smart card 1 interface registers 7 SC1_CFG0 1 SC1_CFG1 X SC1_CFG2 0 SC1_CFG3 X SC1_CFG4 X SC1_INTERFACE 0 SC1_STATUS CC81 Table 9. Smart card 2 interface ...
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Table 13. Common registers for SC1/SC2/SC3/SC4/SC5 7 TIMER_MSB Bit 15 TIMER_LSB Bit 7 CAPTURE_MSB Bit 15 CAPTURE_LSB Bit 7 IO_SELECT X Table 14. Common registers for SC2/SC3/SC4/SC5 7 INTERFACEB X STATUSB X ITDIS IODIS5 Table 15. DC/DC B registers 7 ...
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Registers Table 17. SC1_ CFG0(Config Byte 0 for SC1 ATRERR1 Bit Number Bit Mnemonic 7-6 1-0 5 ATRERR1 4 INSERT1 3 ICARDERR1 2 VCARDERR1 1-0 VCARD1[1:0] Reset value = 0x 1000 0000 Table 18. SC1_CFG1 ...
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Bit Number Bit Mnemonic ART1 5 SHUTDOWNA 4 CARDDET1 3 PULLUP1 2-0 CDS1[2:0] Reset value = 0x X000 1010 Table 19. SC1_CFG2 (Config Byte 2 for SC1 DCK2 7511D–SCR–02/07 Description Automatic Reset Transition Set ...
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Bit Number Bit Mnemonic Description 7 0 This bit must be always at 0. DCK is the first level of prescaler factor. CLK signal is divided by the prescaler value and outputs DCCLK signal. DCCLK is an input for CCLK ...
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Bit Number Bit Mnemonic 4 ICCADJA Reset value = 0x XXX0 XXXX Table 21. SC1_CFG4 (Config Byte 4 for SC1 DEMBOOSTA1 DEMBOOSTA0 Bit Number Bit Mnemonic 7 X 7511D–SCR–02/07 ...
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Bit Number Bit Mnemonic 6-5 DEMBOOSTA[1-0] 4 STEPREGA 3 INT_PULLUP CRST_SEL1 Reset value = 0x X000 0000 Table 22. SC1_INTERFACE (Interface Byte for SC1 IODIS1 CKSTOP1 AT83C26 42 Description DC/DC A ...
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Bit Number Bit Mnemonic IODIS1 5 CKSTOP1 4 CARDRST1 3 CARDC81 2 CARDC41 1 CARDCK1 0 CARDIO1 Reset value = 0x 0110 0000 Table 23. SC1_STATUS (Status Byte for SC1 CC81 CC41 Bit Number Bit ...
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Bit Number Bit Mnemonic 6 CC41 5 CARDIN1 4 VCARD_OK1 VCARD_INT1 1 CRST1 0 CIO1 Reset value = reset value depends on hardware configuration Table 24. SC2_CFG0 () VCARD_INT VCARD_OK 2 2 ATRERR2 AT83C26 ...
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Bit Number Bit Mnemonic 7 VCARD_INT2 6 VCARD_OK2 5 ATRERR2 4 INSERT2 VCARDERR2 1-0 VCARD2[1:0] Reset value = 0x 0000 X000 7511D–SCR–02/07 Description SC2 voltage interrupt This bit is set when VCARD_OK2 bit is set. This bit ...
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Table 25. SC2_CFG1 () SC2_FULL Bit Number Bit Mnemonic Description 7-6 X Set this bit to activate full IO interface on Smart card 2: • • • • 5 SC2_FULL CVCC2 and CVCC3 shall be connected ...
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Table 26. SC2_CFG2 () 7 6 ART2 CRST_SEL2 Bit Number Bit Mnemonic 7 ART2 6 CRST_SEL2 5 CARDRST2 4 CARDCK2 3 CKSTOP2 2-0 CKS2[2:0] Reset value = 0x00001000 Notes: 7511D–SCR–02/ CARDRST2 CARDCK2 CKSTOP2 Description Automatic Reset Transition Set ...
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Table 27. SC3_CFG0 VCARD_INT3 VCARD_OK3 Bit Number Bit Mnemonic 7 VCARD_INT3 6 VCARD_OK3 5 ATRERR3 VCARDERR3 1-0 VCARD3[1:0] Reset value = 0x 000X 0000 AT83C26 ATRERR3 X X Description ...
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Table 28. SC3_CFG2 () 7 6 ART3 X Bit Number Bit Mnemonic 7 ART3 CARDRST3 4 CARDCK3 3 CKSTOP3 2-0 CKS3[2:0] Reset value = 0x 0X00 1000 Notes: 7511D–SCR–02/ CARDRST3 CARDCK3 Description Automatic Reset Transition ...
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Table 29. SC4_CFG0 VCARD_INT4 VCARD_OK4 ATRERR4 Bit Number Bit Mnemonic 7 VCARD_INT4 6 VCARD_OK4 5 ATRERR4 VCARDERR4 1-0 VCARD4[1:0] Reset value = 0x 000X X000 AT83C26 Description ...
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Table 30. SC4_CFG2 () 7 6 ART4 X Bit Number Bit Mnemonic 7 ART4 CARDRST4 4 CARDCK4 3 CKSTOP4 2-0 CKS4[2:0] Reset value = 0x 0X00 1000 Notes: 7511D–SCR–02/ CARDRST4 CARDCK4 Description Automatic Reset Transition ...
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Table 31. SC5_CFG0 VCARD_INT5 VCARD_OK5 Bit Number Bit Mnemonic 7 VCARD_INT5 6 VCARD_OK5 5 ATRERR5 VCARDERR5 1-0 VCARD5[1:0] Reset value = 0x 000X X000 AT83C26 ATRERR5 X X Description ...
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Table 32. SC5_CFG2 () 7 6 ART5 X Bit Number Bit Mnemonic 7 ART5 CARDRST5 4 CARDCK5 3 CKSTOP5 2-0 CKS5[2:0] Reset value = 0x 0X00 1000 Notes: 7511D–SCR–02/ CARDRST5 CARDCK5 Description Automatic Reset Transition ...
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Table 33. TIMER_MSB (Timer MSB for SC1, SC2, SC3, SC4, SC5 Bit 15 Bit 14 Bit Number Bit Mnemonic Description Bits Timer MSB (bits Reset value = 0x 0000 ...
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Table 37. IO_SELECT (Selection byte for IO Bit Number Bit Mnemonic 3-0 IOSEL[3:0] Reset value = 0x XXXX 1000 Table 38. IO Selection IOSEL[3:0] 0000 0001 0010 0011 ...
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Note: AT83C26 input (IO1, IO2, AUX1, AUX2) is selected for a SCIB pin (CIOn, CC4n CC8n), and if the smart card interface is started, the electrical level on the SCIB pin corresponds to the CAR- DIOn, ...
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Table 39. INTERFACEB () CARDC82 CARDIO5 Bit Number Bit Mnemonic CARDC82 5 CARDIO5 4 CARDIO4 CARDIO3/ 3 CARDC42 2 CARDIO2 1-0 DEMBOOSTB[1-0] Reset value = 0x X000 0000 7511D–SCR–02/ CARDIO3/CAR CARDIO4 ...
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Table 40. STATUSB () - Read Only CARDIN2 Bit Number Bit Mnemonic CARDIN2 5 CIO5 4 CIO4 3 CRST3/CC82 2 CIO3/CC42 1 CRST2 0 CIO2 Reset value = reset value depends on hardware configuration ...
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Table 41. ITDIS () 7 6 IODIS5 IODIS4 Bit Number Bit Mnemonic 7 IODIS5 6 IODIS4 5 IODIS3 4 IODIS2 3 ITDIS5 2 ITDIS4 1 ITDIS3 0 ITDIS2 Reset value = 0x 1111 0010 7511D–SCR–02/ IODIS3 IODIS2 ...
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Table 42. DCDCB (Config Interface B Byte VDCB_INT SHUTDOWNB Bit Number Bit Mnemonic 7 SHUTDOWNB 6 VDCB_INT 5 VDCB_OK ICCADJB 2 STEPREGB 1-0 VDCB[1:0] Reset value = 0x 0000 0000 AT83C26 ...
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Table 43. LDO IPLUS5 IPLUS4 IPLUS3 Bit Number Bit Mnemonic 7 IPLUS5 6 IPLUS4 5 IPLUS3 4 IPLUS2 Reset value = 0x 0000 1111 7511D–SCR–02/ IPLUS2 1 ...
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Table 44. SLEW_CTRL_1(Slew control for SC1 and SC2 CCLK2_SLEW_CT CCLK2_SLEW_CT CIO2_SLEW_CT RL1 RL0 Bit Number Bit Mnemonic 7-6 CCLK2_SLEW_CTRL[1-0] 5-4 CIO2_SLEW_CTRL[1-0] 3-2 CCLK1_SLEW_CTRL[1-0] 1-0 CIO1_SLEW_CTRL[1-0] Reset value = 0x 1111 1111 AT83C26 CIO2_SLEW_CT CCLK1_SLEW_CT ...
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Table 45. SLEW_CTRL_2 (Slew control for SC3 and SC4 CCLK4_SLEW_CTR CCLK4_SLEW_CT CIO4_SLEW_CT L1 RL0 Bit Number Bit Mnemonic 7-6 CCLK4_SLEW_CTRL[1-0] 5-4 CIO4_SLEW_CTRL[1-0] 3-2 CCLK3_SLEW_CTRL[1-0] 1-0 CIO3_SLEW_CTRL[1-0] Reset value = 0x 1111 1111 7511D–SCR–02/ CIO4_SLEW_CT CCLK3_SLEW_CTR ...
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Table 46. SLEW_CTRL_3 (Slew control for SC5 Bit Number Bit Mnemonic 7-4 X 3-2 CCLK5_SLEW_CTRL[1-0] 1-0 CIO5_SLEW_CTRL[1-0] Reset value = 0x XXXX 1111 AT83C26 CCLK5_SLEW_CTR Description 0 0: Mode ...
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Electrical Characteristics Absolute Maximum Ratings Ambient Temperature Under Bias: ....................- 40°C to 85°C Storage Temperature: ................................... -65°C to +150°C Voltage on VCC: ........................................ V Voltage on SCIB pins (***): ......... CVSS -0.5V to CVCC + 0.5V Voltage on host interface ...
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Table 48. Host Interface (IO1, IO2, AUX1, AUX2, CLK, A2/CK, A1/RST, INT) Symbol Parameter V Input Low-voltage IL V Input High Voltage IH V Output low voltage OL V Output High Voltage OH Table 49. Host Interface (SCL, SDA, RESET) ...
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Table 51. Smart Card 1 Class B, 3V (CVCC1) (Continued) Symbol Parameter Card Supply Current Overflow: CI _ovf CC ICCADJA = 0 (reset value) Ripple on CVCC Spikes on CVCC Vcardok up Vcardok high level threshold Vcardok Vcardok low level ...
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Table 53. Smart Card 2 Class A, 5V (CVCC2) (Continued) Symbol Parameter T CVCC 0 to valid VLH Table 54. Smart Card 2 Class B, 3V (CVCC2) Symbol Parameter CVCC Smart card voltage Card Supply Current Overflow: CI _ovf CC ...
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Table 56. Smart Card Class A, 5V (CVCC3, CVCC4, CVCC5) (Continued) Symbol Parameter Ripple on CVCC Spikes on CVCC Vcardok up Vcardok high level threshold Vcardok down Vcardok low level threshold T CVCC valid to 0.4V VHL ...
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Table 59. Smart Card Clock (CCLK1, CCLK2, CCLK3, CCLK4, CCLK5) Symbol Parameter V Output low voltage OL V Output High Voltage OH Rise time t R (see Tables 66 to 68) Fall time t F ...
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Table 60. Smart Card n I/Os (CIOn, CC4n, CC8n, CRSTn (Continued) Symbol Parameter t Fall time F Table 61. Card Presence (CPRES1, CPRES2) Symbol Parameter I CPRES1 weak pull-up output current OL1 R CPRES2 ...
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Table 64. Slew rate on CIOn with CVCCn= 3V (n= 5), Mode 2 Symbol Parameter Rise time/ Fall time t with CIOn_SLEW_CTRL[1- (3V) R/F or CIOn_SLEW_CTRL[1-0] = 11(mode auto) Rise time t R with CIOn_SLEW_CTRL[1-0] ...
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Typical Application HOST 4 * Px,y Smart Card Interface CCLK CRST0 CRST1 CLK_OUT XTAL1 XTAL2 MHz VSS VSS 7511D–SCR–02/07 100nF VSS EVCC SCL TWI SDA Px.y RESET INT0 INT IO1,IO2, AUX1, AUX2 A2/CK A1/RST CLK Px.y VSS ...
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Ordering Information Part Number AT83C26-PLTUL AT83C26-PLRUL AT83C26-RKTUL AT83C26-RKRUL Samples Part Number AT83C26-PLTEL AT83C26-RKTEL AT83C26 74 Supply Voltage Temperature Range 3V to 5.5V Industrial green 3V to 5.5V Industrial green 3V to 5.5V Industrial green 3V to 5.5V Industrial green Supply ...
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Package Drawings VQFP48 7511D–SCR–02/07 AT83C26 75 ...
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QFN48 AT83C26 76 7511D–SCR–02/07 ...
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Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 ...