GD82551QM INTEL [Intel Corporation], GD82551QM Datasheet - Page 24

• Manufacturer Part Number: GD82551QM
• Description: Fast Ethernet Multifunction PCI/CardBus Controller
• Manufacturer: INTEL [Intel Corporation]

82551QM — Networking Silicon
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Figure 2. CSR I/O Read Cycle
Figure 3. CSR I/O Write Cycle
Read Accesses: The CPU, as the initiator, drives address lines AD[31:0], the command and byte
enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. As a slave, the 82551QM
controls the TRDY# signal and provides valid data on each data access. The 82551QM allows the
CPU to issue only one read cycle when it accesses the Control/Status Registers, generating a
disconnect by asserting the STOP# signal. The CPU can insert wait states by de-asserting IRDY#
when it is not ready.
CLK
FRAME#
AD
C/BE#
IRDY#
TRDY#
DEVSEL#
STOP#
CLK
FRAME#
AD
C/BE#
IRDY#
TRDY#
DEVSEL#
STOP#
1
I/O RD
1
ADDR
I/O WR
ADDR
2
2
3
BE#
3
DATA
BE#
DATA
4
4
5
5
6
6
7
7
8
8
9
9
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