USB3450-FZG SMSC [SMSC Corporation], USB3450-FZG Datasheet - Page 38

• Manufacturer Part Number: USB3450-FZG
• Description: HI-SPEED USB HOST OR DEVICE PHY WITH UTMI+INTERFACE
• Manufacturer: SMSC [SMSC Corporation]

Revision 0.1 (05-11-05)
7.13
(HS Reset T0)
PARAMETER
TIMING
T0
T1
T2
If the device was in FS mode: then the Link leaves the FS terminations enabled. After the SE0 expires,
the downstream port will assert a J state for one low-speed bit time, and the bus will enter a FS Idle
state (maintained by the FS terminations).
If the device was in HS mode: then the Link must switch to the FS terminations before the SE0 expires
(< 1.25µs). After the SE0 expires, the bus will then enter a HS IDLE state (maintained by the HS
terminations).
Figure 7.8
a HS device is attached to an upstream port, power is asserted to the device and the device sets
XCVRSELECT and TERMSELECT to FS mode (time T1).
V
within normal operational range as defined in the Hi-Speed specification. The assertion of Device
Reset (T0) by the upstream port will initialize the device. By monitoring LINESTATE, the Link state
machine knows to set the XCVRSELECT and TERMSELECT signals to FS mode (T1).
The standard FS technique of using a pull-up resistor on DP to signal the attach of a FS device is
employed. The Link must then check the LINESTATE signals for SE0. If LINESTATE = SE0 is asserted
at time T2 then the upstream port is forcing the reset state to the device (i.e. Driven SE0). The device
will then reset itself before initiating the HS Detection Handshake protocol.
HS Device Attach
BUS
is the +5V power available on the USB cable. Device Reset in
Vbus Valid.
Maximum time from Vbus valid to when the device
must signal attach.
Debounce interval. The device now enters the HS
Detection Handshake protocol.
demonstrates the timing of the USB3450 control signals during a device attach event. When
Table 7.10 Attach and Reset Timing Values
Figure 7.8 Device Attach Behavior
DESCRIPTION
DATASHEET
38
Hi-Speed USB Host or Device PHY With UTMI+ Interface
0 (reference)
T0 + 100ms < T1
T1 + 100ms < T2
Figure 7.8
VALUE
indicates that V
SMSC USB3450
Datasheet
BUS
is