LAN8187I SMSC [SMSC Corporation], LAN8187I Datasheet - Page 32

• Manufacturer Part Number: LAN8187I
• Description: High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX
• Manufacturer: SMSC [SMSC Corporation]

Revision 0.6 (02-24-06)
4.12.1
4.12.2
4.13
4.13.1
Boot Strapping Configuration.
Due to a lower I/O voltage, a lower strapping resistor needs to be used to ensure the strapped
configuration is latched into the PHY device at power-on reset.
Note: For VDDIO operation below +2.5V, SMSC recommends designs add external strapping
I/O Voltage Stability
The I/O voltage the System Designer applies on VDDIO needs to maintain its value with a tolerance
of +/- 10%. Varying the voltage up or down, after the PHY has completed power-on reset can cause
errors in the PHY operation.
The Management Control module includes 3 blocks:
Serial Management Interface (SMI)
The Serial Management Interface is used to control the LAN8187/LAN8187I and obtain its status. This
interface supports registers 0 through 6 as required by Clause 22 of the 802.3 standard, as well as
“vendor-specific” registers 16 to 31 allowed by the specification. Non-supported registers (7 to 15) will
be read as hexadecimal “FFFF”.
At the system level there are 2 signals, MDIO and MDC where MDIO is bi-directional open-drain and
MDC is the clock.
A special feature (enabled by register 17 bit 3) forces the PHY to disregard the PHY-Address in the
SMI packet causing the PHY to respond to any address. This feature is useful in multi-PHY
applications and in production testing, where the same register can be written in all the PHYs using a
single write transaction.
The MDC signal is an aperiodic clock provided by the station management controller (SMC). The MDIO
signal receives serial data (commands) from the controller SMC, and sends serial data (status) to the
SMC. The minimum time between edges of the MDC is 160 ns. There is no maximum time between
edges.
The minimum cycle time (time between two consecutive rising or two consecutive falling edges) is 400
ns. These modest timing requirements allow this interface to be easily driven by the I/O port of a
microcontroller.
The data on the MDIO line is latched on the rising edge of the MDC. The frame structure and timing
of the data is shown in
PHY Management Control
Serial Management Interface (SMI)
Management Registers Set
Interrupt
resistors in addition the internal strapping resistors to ensure proper strapped operation.
Table 4.3 Boot Strapping Configuration Resistors
I/O voltage
3.0 to 3.6
2.0 to 3.0
1.6 to 2.0
Figure 4.6
and
DATASHEET
10k ohm resistor
7.5k ohm resistor
5k ohm resistor
High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX
Pull-up/Pull-down Resistor
Figure
32
4.7.
SMSC LAN8187/LAN8187I
Datasheet