LAN91C96I_07 SMSC [SMSC Corporation], LAN91C96I_07 Datasheet - Page 36
LAN91C96I_07
Manufacturer Part Number
LAN91C96I_07
Description
Non-PCI Single-Chip Full Duplex Ethernet Controller
Manufacturer
SMSC [SMSC Corporation]
Datasheet
1.LAN91C96I_07.pdf
(109 pages)
- Current page: 36 of 109
- Download datasheet (548Kb)
Rev. 03-28-07
AUI
X
X
X
X
1
0
TXENA - Transmit enabled when set. Transmit is disabled if clear. When the bit is cleared the LAN91C96I
will complete the current transmission before stopping. When stopping due to an error, this bit is
automatically cleared.
I/O SPACE - BANK0
This register stores the status of the last transmitted frame. This register value, upon individual transmit
packet completion, is stored as the first word in the memory area allocated to the packet. Packet interrupt
processing should use the copy in memory as the register itself will be updated by subsequent packet
transmissions. The register can be used for real time values (like TXENA and LINK OK). If TXENA is
cleared the register holds the last packet completion status.
TXUNRN - Transmit Under run. Set if Under run occurs, it also clears TXENA bit in TCR. Cleared by
setting TXENA high. This bit should never be set under normal operation.
LINK_OK - State of the 10BASE-T Link Integrity Test. A transition on the value of this bit generates an
interrupt when the LE ENABLE bit in the Control Register is set.
RES – This bit is reserved and will always return a zero(0). CTR_ROL - Counter Roll over. When set one
or more 4 bit counters have reached maximum count (15). Cleared by reading the ECR register.
EXC_DEF - Excessive deferral. When set last/current transmit was deferred for more than 1518 * 2 byte
times. Cleared at the end of every packet sent.
LOST_CARR - Lost carrier sense. When set indicates that Carrier Sense was not present at end of
preamble. Valid only if MON_CSN is enabled. This condition causes TXENA bit in TCR to be reset.
Cleared by setting TXENA bit in TCR.
OFFSET
2
UNRN
DEFR
FDS
TX
TX
0
0
E
X
X
0
0
0
1
FDUPLX
LINK_
BRD
LTX
OK
0
0
X
1
1
1
0
1
EPH STATUS REGISTER
SQET
RES
EPH_LOOP
0
0
1
0
0
0
0
0
DATASHEET
Table 7.1 - Transmit Loop
NAME
16COL
_ROL
CTR
0
0
LOOP
Page 36
X
0
0
0
1
0
MULT
_DEF
EXC
LTX
0
0
SWITCHED ETHERNET
NORMAL CSMA/CD -
- No loopback and No
10BASE-T Driver
CARR
LOST
FULL DUPLEX
MUL
COL
No Loopback
LOOPS AT
0
0
EPH Block
Non-PCI Single-Chip Full Duplex Ethernet Controller
ENDEC
SQET
Cable
READ ONLY
TYPE
LATCOL
SNGL
COL
0
0
WAKEUP
TX_SUC
TO NETWORK
TRANSMITS
0
0
SYMBOL
EPHSR
Yes
Yes
Yes
Yes
SMSC DS – LAN91C96I
No
No
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