LAN9218-MT-E2 SMSC [SMSC Corporation], LAN9218-MT-E2 Datasheet - Page 120

• Manufacturer Part Number: LAN9218-MT-E2
• Description: High-Performance Single- Chip 10/100 Ethernet Controller with HP Auto-MDIX
• Manufacturer: SMSC [SMSC Corporation]

Revision 1.5 (07-18-06)
6.6
SYMBOL
SYMBOL
t
t
t
cycle
t
t
t
t
t
doff
doh
csh
asu
dsu
csl
ah
nCS, nRD
Data Bus
A[7:1]
Note: An RX Data FIFO Direct PIO Burst Read cycle begins when both nCS and nRD are asserted.
PIO writes are used for all LAN9218 write cycles. PIO writes can be performed using Chip Select (nCS)
or Write Enable (nWR). Either or both of these control signals must go high between cycles for the
period specified.
PIO Writes are valid for 16- and 32-bit access. Timing for 16-bit and 32-bit PIO write cycles are
identical with the exception that D[31:16] are ignored during a 16-bit write.
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths.
PIO Writes
DESCRIPTION
Data Buffer Turn Off Time
Data Output Hold Time
DESCRIPTION
Write Cycle Time
nCS, nWR Deassertion Time
Address Setup to nCS, nWR Assertion
Address Hold Time
Data Setup to nCS, nWR Deassertion
nCS, nWR Assertion Time
The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and
deasserted in any order.
Table 6.6 RX Data FIFO Direct PIO Burst Read Cycle Timing
Figure 6.5 PIO Write Cycle Timing
Table 6.7 PIO Write Cycle Timing
DATASHEET
120
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
MIN
MIN
45
32
13
0
0
7
0
TYP
TYP
MAX
MAX
7
SMSC LAN9218
Datasheet
UNITS
UNITS
ns
ns
ns
ns
ns
ns
ns
ns