LAN9218I-MT-E2 SMSC [SMSC Corporation], LAN9218I-MT-E2 Datasheet - Page 54

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LAN9218I-MT-E2

Manufacturer Part Number
LAN9218I-MT-E2
Description
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX & Industrial Temperature Support
Manufacturer
SMSC [SMSC Corporation]
Datasheet
Revision 1.5 (07-18-06)
3.14.3
29:16
BITS
31
30
15
14
13
12
10
11
Reserved. This bit is reserved. Reads 0.
Filtering Fail. When set, this bit indicates that the associated frame failed the address recognizing
filtering.
Packet Length. The size, in bytes, of the corresponding received frame.
Error Status (ES). When set this bit indicates that the MIL has reported an error. This bit is the
Internal logical “or” of bits 11,7,6 and 1.
Reserved. These bits are reserved. Reads 0.
Broadcast Frame. When set, this bit indicates that the received frame has a Broadcast address.
Length Error (LE). When set, this bit indicates that the actual length does not match with the
length/type field of the received frame.
Runt Frame. When set, this bit indicates that frame was prematurely terminated before the collision
window (64 bytes). Runt frames are passed on to the host only if the Pass Bad Frames bit MAC_CR
Bit [16] is set.
Multicast Frame. When set, this bit indicates that the received frame has a Multicast address.
RX Status Format
Host Read
Order
Last
2nd
1st
Figure 3.17 RX Packet Format
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX & Industrial Temperature Support
31
ofs + First Data DWORD
DATASHEET
Optional offset DWORDn
Optional offset DWORD0
Optional Pad DWORD0
Optional Pad DWORDn
Last Data DWORD
DESCRIPTION
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SMSC LAN9218I
Datasheet

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