LAN9311i SMSC [SMSC Corporation], LAN9311i Datasheet - Page 180

• Manufacturer Part Number: LAN9311i
• Description: Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
• Manufacturer: SMSC [SMSC Corporation]

Revision 1.6 (08-18-09)
14.2.1.4
31:24
23:16
BITS
15:8
7:0
TX Data Available Level
The value in this field sets the level, in number of 64 Byte blocks, at which
the
TX Data FIFO free space is greater than this value, a
Available Interrupt (TDFA)
(INT_STS).
TX Status Level
The value in this field sets the level, in number of DWORD’s, at which the
TX Status FIFO Level Interrupt (TSFL)
Status FIFO used space is greater than this value, a
Interrupt (TSFL)
(INT_STS).
RESERVED - This field must be written with 00h for proper operation.
RX Status Level
The value in this field sets the level, in number of DWORD’s, at which the
RX Status FIFO Level Interrupt (RSFL)
Status FIFO used space is greater than this value, a
Interrupt (RSFL)
(INT_STS).
FIFO Level Interrupt Register (FIFO_INT)
This read/write register configures the limits where the RX/TX Data and Status FIFO’s will generate
system interrupts.
TX Data FIFO Available Interrupt (TDFA)
Offset:
will be generated in the
will be generated in the
will be generated in the
068h
DESCRIPTION
DATASHEET
will be generated. When the TX
will be generated. When the RX
Interrupt Status Register
Interrupt Status Register
180
will be generated. When the
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Size:
Interrupt Status Register
RX Status FIFO Level
TX Status FIFO Level
TX Data FIFO
32 bits
TYPE
R/W
R/W
R/W
R/W
SMSC LAN9311/LAN9311i
DEFAULT
48h
00h
00h
00h
Datasheet