PEB2447 SIEMENS [Siemens Semiconductor Group], PEB2447 Datasheet - Page 43

• Manufacturer Part Number: PEB2447
• Description: Memory Time Switch Extended Large MTSXL
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

4.16
Access in a demultiplexed P-interface mode:
Read, address:
Reset value:
FEV7..0
4.17
Access in demultiplexed P-interface mode:
Read, address:
Reset value:
FEV11..0
Table 15
Frame Evaluation Register
CLK / 1.024 MHz Offset Value = FEV11..1
16
Note: Time constant “X” is specified to 0 ns < X < 13 ns (see figure 8)
Semiconductor Group
Frame Evaluation Register Low (FERL)
Frame Evaluation Register High (FERH)
FEV7
Bit 7
Bit 7
0
FEV6
Frame Evaluation Values (bits 7 to 0); refer to FERH;
Frame Evaluation Values; after a frame evaluation procedure
(interrupt ISTA:FEC) these two registers contain the offset between
the SP frame and an evaluated FS0 ... FS5 frame. The evaluation is
performed at the second following rising edge of FS after the
command CMDR:SFE = 1 was programmed.
Note: The device must be synchronized to SP (STAR: PSS = 1) in
Number of clock periods +1
Number of clock periods +1
0
order to generate a correct result in FERL / FERH.
FEV5
0
0E
XX
0F
XX
H
H
FEV4
H
H
0
43
FEV11 FEV10
FEV3
FEV0
0
1
FEV2
Detailed Register Description
FS Rising Edge between
Clock rising edge-X ns and
clock falling edge-X ns
Clock falling edge-X ns
and clock rising edge-X ns
FEV9
FEV1
FEV0
FEV8
Bit 0
Bit 0
PEB 2447
03.97