PEB2466 SIEMENS [Siemens Semiconductor Group], PEB2466 Datasheet - Page 46

• Manufacturer Part Number: PEB2466
• Description: Four Channel Codec Filter with PCM- and m-Controller Interface SICOFI4-mC
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Semiconductor Group
3.5.6
This register contains additional configuration items valid for all 4 channels
MCLK-SEL
CRSH_A
CRSH_B
CHCLK2
VERSION
1)
Bit 7
A crash occurs, if 2 or more channels are programed to transmit (talk) in the same time slot on the same
highway. In this case the crash-bit will be set, and transmission will be disabled for all affected channels.
XR5 Extended Register 5
MCLK-SEL
Selects Master Clock frequency, that has to be applied to pin MCLK
The MCLK signal has to synchronous to the 8 kHz FSC-signal.
0 0:
0 1:
1 0:
1 1:
Crash
0:
1:
Crash on PCM-highway B (line DXB)
0:
1:
Enables Chopper Clock Output to pin CHCLK2
0 0:
0 1:
1 0:
1 1:
This two bit field identifies the actual chip version,
is ‘00’ for Version 1.1, and ‘01’ for Version 1.2
1)
CRSH_A CRSH_B
on PCM-highway A (line DXA)
1536 kHz selected
2048 kHz selected
4096 kHz selected
8192 kHz selected
No crash detected
Crash detected (bad programming in CR5-registers)
No crash detected
Crash detected (bad programming in CR5-registers)
pin CHCLK2 is set to 1
A 512 kHz signal is fed to pin CHCLK2
A 256 kHz signal is fed to pin CHCLK2
A 16384 kHz signal (internal masterclock) is fed to pin
CHCLK2
(at least one of the four channels has to be set to
‘POWER UP’)
46
CHCLK2
Programming the SICOFI
Version
PEB 2466
0
®
-4- C
02.97