LPC47M112_07 SMSC [SMSC Corporation], LPC47M112_07 Datasheet - Page 96

• Manufacturer Part Number: LPC47M112_07
• Description: Enhanced Super I/O Controller with LPC Interface
• Manufacturer: SMSC [SMSC Corporation]

Enhanced Super I/O Controller with LPC Interface
Datasheet
Command/Data
ECP Mode supports two advanced features to improve the effectiveness of the protocol for some applications. The
features are implemented by allowing the transfer of normal 8 bit data or 8 bit commands.
When in the forward direction, normal data is transferred when HostAck is high and an 8 bit command is transferred
when HostAck is low.
The most significant bit of the command indicates whether it is a run-length count (for compression) or a channel
address.
When in the reverse direction, normal data is transferred when PeriphAck is high and an 8 bit command is transferred
when PeriphAck is low. The most significant bit of the command is always zero. Reverse channel addresses are seldom
used and may not be supported in hardware.
Data Compression
The ECP port supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a
peripheral. Run length encoded (RLE) compression in hardware is not supported. To transfer compressed data in ECP
mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo.
Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times
the next byte is to be repeated.
specified number of times. When a run-length count is received from a peripheral, the subsequent data byte is replicated
the specified number of times. A run-length count of zero specifies that only one byte of data is represented by the next
data byte, whereas a run-length count of 127 indicates that the next byte should be expanded to 128 bytes. To prevent
data expansion, however, run-length counts of zero should be avoided.
Pin Definition
The drivers for nStrobe, nAutoFd, nInit and nSelectIn are open-collector in mode 000 and are push-pull in all other
modes.
LPC Connections
The interface can never stall causing the host to hang. The width of data transfers is strictly controlled on an I/O address
basis per this specification. All FIFO-DMA transfers are byte wide, byte aligned and end on a byte boundary. (The
PWord value can be obtained by reading Configuration Register A, cnfgA, described in the next section). Single byte
wide transfers are always possible with standard or PS/2 mode using program control of the control signals.
Interrupts
The interrupts are enabled by serviceIntr in the ecr register.
serviceIntr = 1 Disables the DMA and all of the service interrupts.
serviceIntr = 0
An interrupt is generated when:
1. For DMA transfers: When serviceIntr is 0, dmaEn is 1 and the DMA TC cycle is received.
2. For Programmed I/O:
SMSC DS – LPC47M112
a.
b.(1)
When serviceIntr is 0, dmaEn is 0, direction is 0 and there are writeIntrThreshold or more free bytes in the
FIFO. Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are writeIntrThreshold or
more free bytes in the FIFO.
Enables the selected interrupt condition.
generated immediately when this bit is changed from a 1 to a 0. This can occur during Programmed
I/O if the number of bytes removed or added from/to the FIFO does not cross the threshold.
When serviceIntr is 0, dmaEn is 0, direction is 1 and there are readIntrThreshold or more bytes in the
FIFO.
readIntrThreshold or more bytes in the FIFO.
Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are
Table 45 -Forward Channel Commands (HostAck Low)
Decompression simply intercepts the RLE byte and repeats the following byte the
Reverse Channel Commands (PeripAck Low)
D7
0
1
DATASHEET
Run-Length
(mode 0011 0X00 only)
Channel Address (0-127)
Page 96
D[6:0]
If the interrupting condition is valid, then the interrupt is
Count
(0-127)
Rev. 02-16-07