LPC47M140-NC SMSC [SMSC Corporation], LPC47M140-NC Datasheet - Page 101

• Manufacturer Part Number: LPC47M140-NC
• Description: 128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB
• Manufacturer: SMSC [SMSC Corporation]

6.12 INTERRUPT GENERATING REGISTERS
The LPC47M14x contains on-chip Interrupt Generating Registers to enable external software to generate IRQ1
through IRQ15 on the Serial IRQ Interface. These registers, INT_GEN1 and INT_GEN2 as shown below, are located
in the Logical Device A Runtime Block, at offsets 54h and 55h, respectively, from the Runtime Block base address
setting (set at Index 0x60 and 0x61, Logical Device A Configuration Registers).
Registers INT_GEN1 and INT_GEN2 are enabled to output to the Serial IRQ stream by setting Logical Device A
Configuration Register, at Index 0xF1, Bit [0] to ‘1’. When Bit [0] is set to ‘0’, INT_GEN1 and INT_GEN2 are
prevented from outputting to the Serial IRQ stream.
Writing Bits 0 through 8 to ‘0’ in registers INT_GEN1 and INT_GEN2 enable the corresponding interrupt (INT1
through INT15) to be asserted (made active) in the Serial IRQ stream. Producing an interrupt in the Serial IRQ stream
by writing these bits to ‘0’ overrides other interrupt sources for the Serial IRQ stream. No other functional logic in the
LPC47M14x sets bits in these registers. The asserted interrupt in the Serial IRQ stream from registers INT_GEN1
and INT_GEN2 is removed by writing the corresponding bit to ‘1’.
SMSC DS – LPC47M14X
nINT 15
nINT 7
Bit 7
Bit 7
nINT 14
nINT 6
Bit 6
Bit 6
DEFAULT VALUE
DEFAULT VALUE
nINT 13
nINT 5
ATTRIBUTE
ATTRIBUTE
LOCATION
LOCATION
Bit 5
Bit 5
NAME
NAME
SIZE
SIZE
INT_GEN1 Register
INT_GEN2 Register
nINT 12
nINT 4
Bit 4
Bit 4
Page 101
Runtime Block Offset 54h
Runtime Block Offset 55h
nINT 11
nINT 3
Bit 3
Bit 3
Read/Write
Read/Write
INT_GEN1
INT_GEN2
8 bits
8 bits
0xFF
0xFF
nINT 10
nINT2
Bit 2
Bit 2
nINT 9
nINT1
Bit 1
Bit 1
Reserved
nINT 8
Bit 0
Bit 0
Rev. 03/19/2001