SC26C198C1A PHILIPS [NXP Semiconductors], SC26C198C1A Datasheet - Page 10

• Manufacturer Part Number: SC26C198C1A
• Description: Octal UART with TTL compatibility at 3.3V and 5V supply voltages
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
38.4 KHz baud rate and will signal a change when a transition has
been stable for two rising edges of this clock. Thus a level on the
I/O ports must be stable for 26 s to 52 s. Defining a port as an
output will disable the COS detector at that port. The condition of
the four I/O pins and their COS detectors is available at any time in
the IPR (Input Port Register)
The control of data and COS enable for these ports is through the
I/OPIOR register. This is a read/write register and gives individual
control to the enabling of the change of state detectors and also to
the level driven by I/O pins when programmed to drive the logic level
written to the four lower bits of the I/OPIOR. A read of this register
will indicate the data on the pin at the time of the read and the state
of the enabled COS detectors.
General Purpose Pins
In addition to the I/O ports for each UART four other ports are
provided which service the entire chip. Two are dedicated as inputs
and one as an output. The G
the output. These ports are multiplexed to nearly every functional
unit in the chip. See the registers which describe the multitude of
connections available for these pins. The G
multiplexed output and is controlled by four (4) registers: GPOSR,
GPOR, GPOC and GPOD. The G
the receivers and transmitters, BRG counters and the G
Global Registers
The ”Global Registers”, 19 in all, are driven by the interrupt system.
These are not real hardware devices. They are defined by the
content of the CIR (Current Interrupt Register) as a result of an
interrupt arbitration. In other words they are indirect registers
pointed to by the content of the CIR. The list of global register
follows:
A read of the GRxFIFO will give the content of the RxFIFO that
presently has the highest bid value. The purpose of this system is
to enhance the efficiency of the interrupt system. The global
registers and the CIR update procedure are further described in the
Interrupt Arbitration system
Character Recognition
The character recognition circuits are basically designed to provide
general purpose character recognition. Additional control logic has
been added to allow for Xon/Xoff flow control and for recognition of
the address character in the multi-drop or ”wake–up” mode. This
logic also allows for the generation of an interrupts in either the
general purpose recognition mode or the specific conditions
mentioned above.
Xon Xoff Characters
The programming of these characters is usually done individually.
However a method has been provided to write to all of registers in
one operation. There are ”Gang Load” and a ”Gang Write”
commands provided in the channel A Command Register. When
these commands are executed all registers are programmed with
the same characters. The ”write” command loads a used defined
character; the ’load” command loads the standard Xon/Xoff
characters. Xon is x’11; Xoff x’13’. Any enabling of the Xon/Xoff
functions will use the contents of the Xon and Xoff character
registers as the basis on which recognition is predicated.
1995 May 1
Octal UART with TTL compatibility at 3.3V
and 5V supply voltages
GIBCR
GICR
GITR
GRxFIFO Pointer to the interrupting receiver FIFO
GTxFIFO Pointer to the interrupting transmitter FIFO
The byte count of the interrupting FIFO
Channel number of the interrupting channel
Type identification of interrupting channel
IN
1 and G
IN
0 and G
IN
0 are the input pins; G
OUT
IN
1 pins are available to
0 pin is highly
OUT
0 pin.
OUT
0
345
Multi-drop or Wake up or 9 bit mode
This mode is used to address a particular UART among a group
connected to the same serial data source. Normally it is
accomplished by redefining the meaning of the parity bit such that it
indicates a character as address or data. While this method is fully
supported in the SC26C198 it also supports recognition of the
character itself. Upon recognition of its address the receiver will be
enabled and data pushed onto the RxFIFO.
Further the Address recognition has the ability, if so programmed, to
disable (not reset) the receiver when an address is seen that is not
recognized as its own. The particular features of ”Auto Wake and
Auto Doze” are described in the detail descriptions below.
Note: Care should be taken in the programming of the character
recognition registers. Programming x’00, for example, may result in
a break condition being recognized as a control character. This will
be further complicated when binary data is being processed.
Character Stripping
The MR0 register provides for stripping the characters used for
character recognition. Recall that the character recognition may be
conditioned to control several aspects of the communication.
However this system is first a character recognition system. The
status of the various states of this system are reported in the XISR
and ISR registers. The character stripping of this system allows for
the removal of the specified control characters from the data stream:
two for the Xon /Xoff and one for the wake up. Via control in the
MR0 register these characters may be discarded (stripped) from the
data stream when the recognition system “sees” them or they may
be sent on the RxFIFO. Whether they are stripped or not the
recognition will process them according to the action requested: flow
control, wake up, interrupt generation, etc. Care should be
exercised in programming the stripping option if noisy environments
are encountered. If a normal character was corrupted to an Xoff
character turned off the transmitter and it was then stripped, then the
stripping action could make it difficult to determine the cause of
transmitter stopping.
Interrupt Arbitration and IRQN generation
Interrupt arbitration is the process used to determine that an
interrupt request should be presented to the host. The arbitration is
carried out between the ”Interrupt Threshold” and the ”sources”
whose interrupt bidding is enabled by the IMR. The interrupt
threshold is part of the ICR (Interrupt Control Register) and is a
value programmed by the user. The ”sources” present a value to
the interrupt arbiter. That value is derived from four fields: the
channel number, type of interrupt source, FIFO fill level, and
programmable value. . Only when one or more of these values
exceeds the threshold value in the interrupt control register will the
interrupt request (IRQN) be asserted.
Following assertion of the IRQN the host will either assert
IACKN(Interrupt Acknowledge) or will use the command to ”Update
the CIR”. At the time either action is taken the CIR will capture the
value of the source that is prevailing in the arbitration process. (Call
this value the winning bid)
The value in the CIR is the central quantity that results from the
arbitration. It contains the identity of the interrupting channel, the
type of interrupt in that channel (RxD, TxD, COS etc.) the fill levels
of the RxD or TxD FIFOs and , in the case of an RxD interrupt an
indicator of error data or good data. It also drives the Global
Registers associated with the interrupt. Most importantly it drives
the modification of the Interrupt Vector.
The arbitration process is driven by the Sclk. It scans the 10 bits of
the arbitration bus at the Sclk rate developing a value for the CIR
SC26C198 SC68C198
SC26L198 SC68L198
Product specification