ADM705_08 AD [Analog Devices], ADM705_08 Datasheet - Page 5

• Manufacturer Part Number: ADM705_08
• Description: Supervisory Circuits
• Manufacturer: AD [Analog Devices]

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 3. Pin Function Descriptions
Mnemonic
MR
V
GND
PFI
PFO
WDI
NC
RESET
WDO
RESET
CC
Figure 3. ADM705/ADM706 PDIP/SOIC
GND
V
MR
PFI
CC
1
2
3
4
(Not to Scale)
ADM705/
ADM706
Pin Configuration
TOP VIEW
3
4
6
N/A
N/A
ADM705/
ADM706
(PDIP, SOIC)
1
2
5
7
8
8
7
6
5
PFO
WDO
RESET
WDI
Pin Number
ADM707/
ADM708
(PDIP, SOIC)
1
2
3
4
5
N/A
6
7
N/A
8
ADM708
(MSOP)
3
4
5
6
7
N/A
8
1
N/A
2
GND
Figure 4. ADM707/ADM708 PDIP/SOIC
V
MR
PFI
CC
1
2
3
4
NC = NO CONNECT
Description
Manual Reset Input. When this pin is taken below 0.8 V, a reset is generated.
MR can be driven from TTL, CMOS logic, or from a manual reset switch as it is
internally debounced. An internal 250 μA pull-up current holds the input high
when floating.
5 V Power Supply Input.
0 V Ground Reference for All Signals.
Power-Fail Input. PFI is the noninverting input to the power-fail comparator.
When PFI is less than 1.25 V, PFO goes low. If unused, PFI should be connected
to GND or V
Power-Fail Output. PFO is the output from the power-fail comparator. It goes
low when PFI is less than 1.25 V.
Watchdog Input. WDI is a three-level input. If WDI remains either high or low
for longer than the watchdog timeout period, the watchdog output (WDO)
goes low. The timer resets with each transition at the WDI input. Either a high-
to-low or a low-to-high transition clears the counter. The internal timer is also
cleared whenever reset is asserted. The watchdog timer is disabled when WDI
is left floating or connected to a three-state buffer.
No Connect.
Logic Output. RESET goes low for 200 ms when triggered. It can be trig-
gered either by V
manual reset input (MR). RESET remains low whenever V
threshold (4.65 V in ADM705/ADM707, 4.40 V in ADM706/ADM708). It remains
low for 200 ms after V
high. A watchdog timeout does not trigger RESET unless WDO is connected to MR.
Watchdog Output. WDO remains low until the watchdog timer is cleared. WDO
also goes low during low line conditions. Whenever V
threshold, WDO goes low if the internal WDO remains low. As soon as V
above the reset threshold, WDO goes high.
Logic Output. RESET is an active high output suitable for systems that use
active high reset logic. It is the inverse of RESET.
(Not to Scale)
Rev. G | Page 5 of 12
ADM707/
ADM708
Pin Configuration
TOP VIEW
CC
8
7
6
5
.
PFO
RESET
RESET
NC
CC
being below the reset threshold or by a low signal on the
CC
goes above the reset threshold or MR goes from low to
ADM705/ADM706/ADM707/ADM708
RESET
RESET
V
MR
CC
Figure 5. ADM708 MSOP
1
2
3
4
NC = NO CONNECT
(Not to Scale)
Pin Configuration
ADM708
TOP VIEW
CC
is below the reset
CC
is below the reset
8
7
6
5
GND
NC
PFO
PFI
CC
goes