V385 ICST [Integrated Circuit Systems], V385 Datasheet

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V385

Manufacturer Part Number
V385
Description
8-BIT LVDS TRANSMITTER FOR VIDEO
Manufacturer
ICST [Integrated Circuit Systems]
Datasheet

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V385 Datasheet
General Description
The V385 transmitter converts 28 bits of 3.3 V
CMOS/TTL into 4 Low Voltage Differential Signaling
(LVDS) data streams while the transmit clock input is
transmitted in parallel with the data streams over a fifth
LVDS link. The V385 can be programmed for rising
edge or falling edge clocks through pin R_FB.
ICS manufactures a large variety of video application
devices. Consult ICS for all of your video application
requirements.
Pin Assignment
I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m
TxIN10
TxIN11
TxIN12
TxIN13
TxIN14
TxIN15
TxIN16
TxIN17
TxIN18
TxIN19
TxIN20
TxIN21
TxIN22
TxIN23
TxIN24
TxIN25
TxIN5
TxIN6
TxIN7
TxIN8
TxIN9
R_FB
GND
GND
GND
V385
8-B
VCC
VCC
VCC
IT
56-pin TSSOP
10
11
12
13
14
15
16
17
18
19
1
2
3
4
5
6
7
8
9
20
21
22
23
24
25
26
27
28
LVDS T
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
LVDS_GND
LVDS_VCC
LVDS_GND
LVDS_GND
PLL_GND
PLL_VCC
PLL_GND
PWRDWN
TxIN4
TxIN3
TxIN2
GND
TxIN1
TxIN0
TxIN27
TxOUT0-
TxOUT0+
TxOUT1-
TxOUT1+
TxOUT2-
TxOUT2+
TxCLKOUT-
TxCLKOUT+
TxOUT3-
TxOUT3+
TxCLKIN
TxIN26
GND
RANSMITTER FOR
1
Features
Block Diagram
Red, Green, Blue
Pin and function compatible with the National
DS90C385, TI SN65LVDS93 and THine
THC63LVDM83
Convert 28 bits of 3.3 V CMOS/TTL into 4 LVDS
streams
Up to 2.38 Gbps throughput or 297.5 Megabytes/sec
bandwidth
Wide clock frequency range from 20 MHz to 85 MHz
Spread spectrum compatible
Supports VGA, SVGA, XGA, and SXGA
LVDS voltage swing of 350 mV for low EMI
On-chip PLL requires no external components
Single 3.3 V low-power CMOS design
Programmable rising or falling edge strobe
Power-down control function
Compatible with TIA/EIA-644 LVDS standards
Packaged in a 56-pin TSSOP (Pb free available)
DATA ENABLE
CONTROL
PWRDWN
HSYNC
VSYNC
CLOCK
V
R_FB
IDEO
24
TTL to
LVDS
PLL
3/30/05
Revision 1.6
TxOUT0+
TxOUT0-
TxOUT1+
TxOUT1-
TxOUT2+
TxOUT2-
TxOUT3+
TxOUT3-
TxCLKOUT+
TxCLKOUT-

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V385 Summary of contents

Page 1

... CMOS/TTL into 4 Low Voltage Differential Signaling (LVDS) data streams while the transmit clock input is transmitted in parallel with the data streams over a fifth LVDS link. The V385 can be programmed for rising edge or falling edge clocks through pin R_FB. ICS manufactures a large variety of video application devices ...

Page 2

... Ground LVDS_GND V385 Datasheet • Str • • IDEO Pin Description/Name 3 ...

Page 3

... TxIn4 External Components The V385 requires no external components. V385 Datasheet • Str • • ...

Page 4

... RANSMITTER FOR Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the V385. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. ...

Page 5

... Thermal Resistance Junction to Case V385 Datasheet • Str • • ...

Page 6

... Figure AC3. Phase Lock Loop Set Time V385 Datasheet • Str • • ...

Page 7

... Figure AC5. Transmitter LVDS Output Pulse Position Measurement V385 Datasheet • Str • • ...

Page 8

... V385 Datasheet • Str • • IDEO ...

Page 9

... • Str • • IDEO Package Temperature Tubes 56-pin TSSOP 0 to +70° C 56-pin TSSOP 0 to +70° C Tubes 56-pin TSSOP 0 to +70° C 56-pin TSSOP 0 to +70° C Tubes 56-pin TSSOP 0 to +70° C 56-pin TSSOP 0 to +70° Notes Replaced by V385AGLF Replaced by V385AGLFT 3/30/05 Revision 1.6 ...

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