MAX4358ECE MAXIM [Maxim Integrated Products], MAX4358ECE Datasheet - Page 28

• Manufacturer Part Number: MAX4358ECE
• Description: 32 x 16 Nonblocking Video Crosspoint Switch with On-Screen Display Insertion and I/O Buffers
• Manufacturer: MAXIM [Maxim Integrated Products]

32 x 16 Nonblocking Video Crosspoint Switch
with On-Screen Display Insertion and I/O Buffers
28
21, 23, 25, 27, 29, 31, 33, 35, 37,
22, 24, 26, 28, 30, 32, 34, 72, 73,
75, 77, 79, 81, 83, 85, 87, 89, 91,
2, 4, 6, 8, 10, 12, 14, 16, 18, 20,
76, 80, 84, 88, 92, 96, 100, 104,
1, 3, 5, 7, 9, 11, 13, 15, 17, 19,
39, 41, 43, 45, 127, 129, 131,
107, 108, 109, 126, 128, 130,
36, 74, 78, 82, 86, 90, 94, 98,
110, 111, 112, 113, 114, 115,
116, 117, 118, 119, 120, 121,
133, 135, 137, 139, 141, 143
132, 134, 136, 138, 140, 142
93, 95, 97, 99, 101, 103, 105
______________________________________________________________________________________
122, 123, 124, 125
38, 40, 42, 44
102, 106
55–70
PIN
144
46
47
48
49
50
51
52
53
54
71
OSDKEY0–
OSDFILL15
OSDKEY15
–OSDFILL0
IN0–IN31
UPDATE
OUT15
RESET
OUT0–
NAME
AGND
A3–A0
DGND
MODE
AOUT
DOUT
SCLK
V
V
DIN
V
CE
CC
DD
EE
Buffered Analog Inputs
Analog Ground
Positive Analog Supply. Bypass each pin with a 0.1µF capacitor to AGND.
Connect a single 10µF capacitor from one V
Address Programming Inputs. Connect to DGND or V
for individual output address mode. See Table 4.
Digital Ground
Address Recognition Output. AOUT drives low after successful chip address
recognition.
Serial Interface Mode Select Input. Drive high for Complete Matrix Mode
(Mode 1), or drive low for Individual Output Address Mode (Mode 0).
Serial Data Input. Data is clocked-in on the falling edge of SCLK.
Serial Clock Input
Update Input. Drive UPDATE low to transfer data from Mode Registers to the
switch matrix.
Asynchronous Reset Input/Output. Drive RESET low to initiate hardware reset.
All analog outputs are disabled. Additional power-on reset delay may be set
by connecting a small capacitor from RESET to DGND.
Clock Enable Input. Drive low to enable the serial data interface.
Serial Data Output. In Complete Matrix Mode, data is clocked through the 112-
bit Matrix Control shift register. In Individual Output Address Mode, data at DIN
passes directly to DOUT.
Digital Control Input. Control for the fast 2:1 OSD Insertion multiplexer routing
signal to output buffers. A logic high routes programmed IN_ analog input
signal to output buffer. A logic low routes the dedicated OSDFILL_ input to
corresponding output buffer.
Digital Logic Supply. Bypass V
Buffered Analog Outputs. Gain is individually programmable for A
A
impedance). On power-up, or assertion of RESET, all outputs are disabled.
Negative Analog Supply. Bypass each pin with a 0.1µF capacitor to AGND.
Connect a single 10µF capacitor from one V
Dedicated OSD Analog Signal Buffered Inputs. For each output buffer
amplifier. OSDFILL
the corresponding OSDKEY
V
= +2V/V via the serial interface. Outputs may be individually disabled (high
i
input signal is routed to output buffer amplifier OUT
i
is low.
DD
FUNCTION
with a 0.1µF capacitor to DGND.
CC
EE
pin to AGND.
pin to AGND.
Pin Description
DD
to select the address
V
= +1V/V or
i
when