SX1501 SEMTECH [Semtech Corporation], SX1501 Datasheet
SX1501
Related parts for SX1501
SX1501 Summary of contents
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... PLD to give more flexibility and reduce external logic gates used for standard applications. The SX1501, SX1502 and SX1503 have the ability to generate mask-programmable interrupts based on falling/rising edge of any of its GPIO lines. A dedicated pin indicates to a host controller that a state change occurred in one or more of the GPIO lines ...
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... ETAILED ESCRIPTION 4.1 SX1501 4-channel GPIO 4.2 SX1502 8-channel GPIO 4.3 SX1503 16-channel GPIO 4.4 Reset (NRESET) 2 4.5 2-Wire Interface (I C) 4.5.1 WRITE 4.5.2 READ 4.5.3 READ - STOP separated format (SX1501 and SX1502 only) 4.6 Interrupt (NINT) 4.7 Programmable Logic Functions (PLD) 4.7.1 SX1501 4.7.2 SX1502 4.7.3 SX1503 4.7.4 Tutorial ONFIGURATION EGISTERS 5.1 SX1501 4-channel GPIO 5 ...
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... QFN-UT 28-pin Outline Drawing 7.4 QFN-UT 28-pin Land Pattern 7.5 TSSOP 20-pin Outline Drawing 7.6 TSSOP 20-pin Land Pattern 7.7 TSSOP 28-pin Outline Drawing 7.8 TSSOP 28-pin Land Pattern .............................................................................................................. 33 OLDERING ROFILE nd Rev 7 – 2 Oct. 2008 4/8/16 Channel Low Voltage GPIO ..................................................................................................... 29 3 SX1501/SX1502/SX1503 www.semtech.com ...
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... Leave open, not connected - Leave open, not connected - Connect to VCC1 P Ground Pin - Leave open, not connected - Leave open, not connected 2 C interface Table 1 – SX1501 Pin Description SDA NC1 SCL GND (PAD) I/O[0] Figure 1 – SX1501 QFN-UT-20 Pinout 4 SX1501/SX1502/SX1503 NC3 VDDM NC2 ADDR NINT www.semtech.com ...
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... I/O[5], at power-on configured as an input P Supply voltage for Bank B I/O[4-7] P Ground Pin (*1) DIO I/O[6], at power-on configured as an input (*1) DIO I/O[7], at power-on configured as an input 2 C interface Table 2 – SX1502 Pin Description SDA NC1 SCL GND (PAD) I/O[0] Figure 2 – SX1502 QFN-UT-20 Pinout 5 SX1501/SX1502/SX1503 I/O[4] VDDM NC2 ADDR NINT www.semtech.com ...
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... I C serial clock line (*1) DIO I/O[0], at power-on configured as an input (*1) DIO I/O[1], at power-on configured as an input 2 C interface Table 3 – SX1503 Pin Description 1 GND 2 I/O[2] TOP VIEW 3 I/O[3] GND VCC1 4 (PAD) I/O[4] 5 I/O[5] 6 GND 7 Figure 3 – SX1503 QFN-UT-28 Pinout 6 SX1501/SX1502/SX1503 21 GND 20 I/O[13] I/O[12] 19 VCC2 18 I/O[11] 17 I/O[10] 16 GND 15 www.semtech.com ...
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... VCC1,2 >= 2V (1) VCC1,2 < Assuming no active pull-up/down - - - VCC1,2 >= 2V VCC1,2 < 2V VCC1,2 >= 2V VCC1,2 < 2V VCC1,2 >= 2V VCC1,2 < 2V Cf. Figure 9 - VDDM >= 2V VDDM < 2V From input data change 7 SX1501/SX1502/SX1503 Min Max Unit - 0.4 6 0.4 6 1500 V - 300 V - 200 V -40 +85 ° C -40 +125 ° ...
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... Conditions From RegInterruptSource clearing - VDDM >= 2V VDDM < Cf. Figure 7 Cf. Figure 7 Cf. Figure 7 Cf. Figure 7 Cf. Figure ( interface as described by Philips specifications. - VDDM >= 2V VDDM < VDDM >= 1.3V VDDM < 1. SX1501/SX1502/SX1503 Min Typ Max Unit - - 0 0.7* - 5.5 VDDM 0.3* -0.4 - VDDM 0. VDDM -1 0.7 - 0.9 - VDDM ...
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... VDDM = 5.5V (VCC1,2 < VBOOST) VDDM = 1.2V (VCC1,2 < VBOOST) VCC1 = VBOOST VCC1 = 1.2V VCC2 = VBOOST SX1502 VCC2 = 1.2V VCC2 = VBOOST SX1503 VCC2 = 1.2V VCC1,2 >= VBOOST VCC1,2 < VBOOST VCC1,2 >= VBOOST VCC1,2 < VBOOST VCC1,2 >= VBOOST VCC1,2 < VBOOST VDDM >= VBOOST VDDM < VBOOST 9 SX1501/SX1502/SX1503 Min Typ Max Unit (7) 20+0.1C - 300 400 0.1*VDDM ...
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... IDDM (uA) 1 3.2 VOL vs. IOL 0.15 0.1 VOL (V) 0. Doesn’t vary significantly with temperature nd Rev 7 – 2 Oct. 2008 4/8/16 Channel Low Voltage GPIO IDDM vs VDDM VDDM (V) VOL vs IOL (VCC1,2=1.2V, all IOs) 1.5 4 IOL (mA) 10 SX1501/SX1502/SX1503 90° C -40° Tamb 7.5 9 www.semtech.com ...
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... Doesn’t vary significantly with temperature 5.5 5.4 5.3 VOH (V) 5.2 5 Doesn’t vary significantly with temperature nd Rev 7 – 2 Oct. 2008 4/8/16 Channel Low Voltage GPIO VOL vs IOL (VCC1,2=5.5V, High Sink IOs IOL (mA) VOH vs IOH (VCC1,2=1.2V) 0.2 0.6 0.4 0.8 IOH (mA) VOH vs IOH (VCC1,2=5.5V) 10 IOH (mA) 11 SX1501/SX1502/SX1503 * Tamb Tamb 1 * Tamb 20 www.semtech.com ...
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... ICC (uA) 300 200 100 0 0.4 0.8 1.2 1.6 0 ICC1+ICC2 vs VCC1,2 (VDDM = 5.5V) 500 400 ICC (uA) 300 200 100 0 0.4 0.8 1.2 1 Rev 7 – 2 Oct. 2008 4/8/16 Channel Low Voltage GPIO Boost Mode ON 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 VCC1,2 (V) Boost Mode ON 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 VCC1,2 (V) 12 SX1501/SX1502/SX1503 Tamb -40°C 90°C Tamb -40°C 90°C www.semtech.com ...
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... ADVANCED COMMUNICATIONS & SENSING LOCK ETAILED ESCRIPTION 4.1 SX1501 4-channel GPIO VDDM Reset NRESET SCL Input Filter SDA ADDR 4.2 SX1502 8-channel GPIO VDDM Reset NRESET SCL Input Filter SDA ADDR nd Rev 7 – 2 Oct. 2008 4/8/16 Channel Low Voltage GPIO 4-Bit Bus ...
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... Reset (NRESET) The SX1501, SX1502 and SX1503 generate their own power on reset signal after a power supply is connected to the VDDM pin. The reset signal is made available for the user at the pin NRESET. The rising edge of the NRESET indicates that the startup sequence of the SX1501, SX1502 or SX1503 has finished. NRESET must be connected to VDDM (or greater) either directly, or via a resistor ...
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... Version 2.1 dated January, 2000. The SX1501, SX1502 and SX1503 have respectively 12, 16, and 31 user-accessible internal 8-bit registers. The I the slave address has been sent to the SX1501, SX1502 or SX1503 enabling slave transmitter/receiver, any register can be written or read independently of each other. While there is no auto increment/decrement capability in the SX1501 and SX1502 I access the next register independent of which register you begin accessing ...
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... READ - STOP separated format (SX1501 and SX1502 only) When operating SX1501 or SX1502, stop-separated reads can also be used. This format allows a master to set up the register address pointer for a read and return to that slave at a later time to read the data. In this format the slave address followed by a write command are sent after a start [S] condition. The slave then acknowledges it is being addressed, and the master responds with the 8-bit register address ...
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... Programmable Logic Functions (PLD) The SX1501, SX1502 and SX1503 offer a unique fully programmable logic functions like a PLD to give more flexibility and reduce external logic gates used for standard applications. Since the whole truth table is fully programmable, the SX1501, SX1502, and SX1503 can implement combinatory functions ranging from the basic AND/OR gates to the most complicated ones with up to four 3-to1 PLDs or two 3-to-2 PLDs which can also be externally cascaded if needed ...
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... ADVANCED COMMUNICATIONS & SENSING 4.7.2 SX1502 The SX1502 I/Os can be configured as per the SX1501, and can additionally be configured to provide a 2-to-1 logic function on I/O[4-6], 3-to-1 logic function on I/O[4-7], or 3-to-2 logic decode on I/O[0-4]. RegPLDMode 5:4 1 GPIO 00 01 GPIO 00 10 GPIO 00 11 GPIO 01 00 GPIO 01 01 GPIO 01 10 GPIO 01 11 GPIO ...
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... ADVANCED COMMUNICATIONS & SENSING 4.7.4 Tutorial The generic method described in this paragraph can be applied to any of the SX1501, SX1502 or SX1503. Example: We want to implement an AND gate between I/O[0] and IO[1] on SX1502 1. Identify in the tables above the RegPLDMode setting to be programmed. What we need corresponds to the second line of the SX1502 PLD Table => RegPLDMode = “xx00xx01” ...
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... RegPLDMode 0x11 RegPLDTable0 0x12 RegPLDTable1 0x13 RegPLDTable2 0x14 RegPLDTable3 0x15 RegPLDTable4 0xAB RegAdvanced *Bits set as output take “1” as default value. Table 12 – SX1501 Configuration Registers Overview Addr Name Default 0x00 RegData 0xFF 0x01 RegDir 0xFF 0x02 RegPullUp 0x00 0x03 0x00 ...
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... RegPLDTable0 0x00 0x12 RegPLDTable1 0xXX 0x13 RegPLDTable2 0x00 0x14 0xXX RegPLDTable3 0x15 RegPLDTable4 0xXX 0xAB RegAdvanced 0x00 Table 13 – SX1501 Configuration Registers Description 5.2 SX1502 8-channel GPIO Address Name 0x00 RegData 0x01 RegDir 0x02 RegPullUp 0x03 RegPullDown 0x04 Reserved 0x05 RegInterruptMask 0x06 ...
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... Value to be output on I/O[3] when I/O[2:0] = 110 5 Value to be output on I/O[3] when I/O[2:0] = 101 4 Value to be output on I/O[3] when I/O[2:0] = 100 3 Value to be output on I/O[3] when I/O[2:0] = 011 2 Value to be output on I/O[3] when I/O[2:0] = 010 22 SX1501/SX1502/SX1503 00 : None 01 : Rising 10 : Falling 11 : Both 00 : None 01 : Rising 10 : Falling 11 : Both Applies only when PLDModeHigh is set to PLD 2- to-1 mode ...
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... PLD truth table 2 for Bank A I/O[7:0] PLD truth table 3 for Bank B I/O[15:8] PLD truth table 3 for Bank A I/O[7:0] PLD truth table 4 for Bank B I/O[15:8] PLD truth table 4 for Bank A I/O[7:0] Advanced settings register 23 SX1501/SX1502/SX1503 Applies only when PLDModeLow is set to PLD 3- to-2 mode Applies only when PLDModeLow is set to PLD 3- to-2 mode ...
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... No event has occured on this event has occured on this IO (an edge as configured in relevant RegSense 7:0 register occured). Writing '1' clears the bit in RegEventStatusB and in RegInterruptSourceB if relevant. If the edge sensitivity of the IO is changed, the bit(s) will be cleared automatically 24 SX1501/SX1502/SX1503 Description 00 : None 01 : Rising 10 : Falling 11 : Both 00 : None ...
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... Value to be output on I/O[7] when I/O[6:4] = 010 1 Value to be output on I/O[7] when I/O[6:4] = 001 0 Value to be output on I/O[7] when I/O[6:4] = 000 7 Value to be output on I/O[11] when I/O[10:8] = 111 25 SX1501/SX1502/SX1503 Description Applies only when PLDModeHighB is set to PLD 2-to-1 mode Applies only when PLDModeLowB is set to PLD 2-to-1 mode Applies only when PLDModeHighA is set to PLD ...
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... OFF.RegInterruptSource must be manually cleared directly or via RegEventStatus 1: ON.RegInterruptSource is automatically cleared when RegDataB or RegDataA is read Boost Mode (Cf. §2.2. OFF Reserved. Must be set to 0 (default value) 26 SX1501/SX1502/SX1503 Description PLDModeLowB is set to PLD 3-to-1 mode Applies only when PLDModeLowA is set to PLD 3-to-1 mode Applies only when PLDModeLowB is set to PLD ...
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... SDA ADDR GND Figure 12 - Typical Application Schematic VCCx VBAT VCCx VLED SX1501/2/3 R IOx IOL * LED colour/technology dependent Figure 13 – Typical LED Operation RegDir[x] “0” (Output) Table 18 – LED ON/OFF Control 27 SX1501/SX1502/SX1503 2.5V VCC1 5V 5V I/O[0] I/O[1] I/O[2] I/O[3] 1.2V VCC2 I/O[4] I/O[5] I/O[6] I/O[7] NINT * RegData[x] “0” “1” ...
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... I/O set to “0”) or 48mA (both I/Os set to “0”) => 3 LED intensity steps ( 4 steps with 3 I/Os, 5 steps with 4 I/Os, etc) 6.3 Keypad Implementation SX1501, SX1502, and SX1503 can be used to implement keypad applications up to 8x8 matrix (i.e. 64 keys) Example: We want to implement a 4x4matrix keypad on SX1502 IO[7-0] as inputs with internal pull-ups enabled Figure 14 – 4x4 keypad connection to SX1502 1. Set all I/Os as inputs with internal pull-up (RegDir = 0xFF, RegPullUp = 0xFF) 2. Set NINT to be triggered on any IO’ ...
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... ACKAGING NFORMATION 7.1 QFN-UT 20-pin Outline Drawing QFN-UT 20-pin mm, 0.4 mm pitch Figure 15 - Packaging Information – QFN-UT 20-pin Outline Drawing 7.2 QFN-UT 20-pin Land Pattern Figure 16 - Packaging Information – QFN-UT 20-pin Land Pattern nd Rev 7 – 2 Oct. 2008 SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO 29 www.semtech.com ...
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... ADVANCED COMMUNICATIONS & SENSING 7.3 QFN-UT 28-pin Outline Drawing QFN-UT 28-pin mm, 0.4 mm pitch Figure 17 - Packaging Information – QFN-UT 28-pin Outline Drawing 7.4 QFN-UT 28-pin Land Pattern Figure 18 - Packaging Information – QFN-UT 28-pin Land Pattern nd Rev 7 – 2 Oct. 2008 SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO 30 www.semtech.com ...
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... ADVANCED COMMUNICATIONS & SENSING 7.5 TSSOP 20-pin Outline Drawing Figure 19 - Packaging Information – TSSOP 20-pin Outline Drawing 7.6 TSSOP 20-pin Land Pattern Figure 20 - Packaging Information – TSSOP 20-pin Land Pattern nd Rev 7 – 2 Oct. 2008 SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO 31 www.semtech.com ...
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... ADVANCED COMMUNICATIONS & SENSING 7.7 TSSOP 28-pin Outline Drawing Figure 21 - Packaging Information – TSSOP 28-pin Outline Drawing 7.8 TSSOP 28-pin Land Pattern Figure 22 - Packaging Information – TSSOP 28-pin Land Pattern nd Rev 7 – 2 Oct. 2008 SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO 32 www.semtech.com ...
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... ADVANCED COMMUNICATIONS & SENSING OLDERING ROFILE The soldering reflow profile for the SX1501, SX1502 and SX1503 is described in the standard IPC/JEDEC J- STD-020C. For detailed information please go to Figure 23 - Classification Reflow Profile (IPC/JEDEC J-STD-020C) nd Rev 7 – 2 Oct. 2008 SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO http://www ...
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... Contact Information Semtech Corporation Advanced Communications and Sensing Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 Fax: (805) 498-3804 nd Rev 7 – 2 Oct. 2008 SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO 34 www.semtech.com ...