TDA5153BG PHILIPS [NXP Semiconductors], TDA5153BG Datasheet - Page 15

• Manufacturer Part Number: TDA5153BG
• Description: Pre-amplifier for Hard Disk Drive HDD with MR-read/inductive write heads
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Notes
1. Not used bits in the registers (indicated by X) are don’t care. Default data, initialized at power-up, is zero in all
2. V
1997 Jul 02
0
0
0
0
0
1
1
1
1
a7 a6 a5 a4 0
A7 A6 A5 A4 A3 A2 A1 A0
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
registers. For V
LSB of the test mode register and b2 is the data bit d2 of the compensation register.
th
0
1
1
1
1
0
0
0
1
programming uses both test mode register and compensation capacitor register. d0 in the formula above is the
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
CC
0
0
0
0
0
0
0
0
0
< 2.5 V, the register contents are not guaranteed.
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
MR current DAC register:
write current DAC register:
servo write register:
test mode register:
compensation capacitor register:
high frequency gain attenuator register:
high-frequency gain boost register:
settle time register:
chip ID register:
when a0 = 1, data from the register with address a7 to a4 is read out on
SDATA
I
I
MR
WR
(d0, d1) = (0, 0) = one head
(d0, d1) = (1, 1) = all heads
(d2,d1,d0) = (0,0,0) = not in test mode
(d2,d1,d0) = (0,0,1) = read head test (I
(d2,d1,d0) = (0,1,0) = read head test (I
(d2,d1,d0) = (0,1,1) = temperature monitor
(d2,d1,d0) = (1, X, d0) = thermal asperity detection
equivalent differential capacitance:
nominal pole frequency:
nominal zero frequency:
settle time:
V
ID
th
=
=
=
=
0.5
8 d3
10 k
--------------- -
R
210
ext
t
10 k
--------------- -
+
+
st
R
4 d2
560 d0
ext
=
15
2
20
+
+
+
------------------------------------------------------------------------- -
2 d1
16 d4
+
10
4 d2
280 b2
------------------------------------------------------------------------------ -
8 d3
------------------------------------------------------------------------------ -
8 d3
+
16 d4
+
DESCRIPTION
+
+
1 d0
+
+
2 d1
8 d3
4 d2
4 d2
800 MHz
1
800 MHz
+
, d3 to d0 are preset to (0, 0, 1, 1)
V
4 d2
8 d3
+
+
MR1
MR2
, see note 2
+
+
1 d0
4 d2
2 d1
2 d1
= I
= 5 mA fixed)
+
+
2 d1
MR2
4 d2
+
+
+
+
1
2 d1
)
1 d0
1 d0
+
+
s
1 d0
Preliminary specification
2 d1
+
1 d0
+
TDA5153
1 d0
2 pF
mA
mA