SX8724 SEMTECH [Semtech Corporation], SX8724 Datasheet - Page 11

• Manufacturer Part Number: SX8724
• Manufacturer: SEMTECH [Semtech Corporation]

ADVANCED COMMUNICATIONS & SENSING
GPIO
The GPIO block is a multipurpose 4 bit input/output port. In addition to digital behavior, D0 and D1 pins can be
programmed as analog pins in order to be used as output (reference voltage monitoring) and input for an
external reference voltage (For further details see Figure 14, Figure 15, Figure 16 and Figure 17). Each port
terminal can be individually selected as digital input or output.
The direction of each bit within the GPIO block (input only or input/output) can be individually set using the 4
MSB bits of the RegOut register. If D[x]_DIR = 1, both the input and output buffer are active on the
corresponding GPIO block pin. If D[x]_DIR = 0, the corresponding GPIO block pin is an input only and the
output buffer is in high impedance. After power on reset the GPIO block pins are in input/output mode
(D[x]_DIR are reset to 1)
The input values of GPIO block are available in RegIn register (read only). Reading is always direct – there is
no debounce function in the GPIO block. In case of possible noise on input signals, an external hardware filter
has to be realized. The input buffer is also active when the GPIO block is defined as output and the effective
value on the pin can be read back.
Data stored in the 4 LSB bits of RegOut register are outputted at GPIO block if D[x]_DIR = 1. The default values
after power on reset is low (0).
The digital pins are able to deliver a driving current up to 8 mA.
When the bits VREF_D0_OUT and VREF_D1_IN in the RegMode register are set to 1 the D0 and D1 pins
digital behavior are automatically bypassed in order to either input or output the voltage reference signals.
V1.23 © 2009 Semtech Corp.
D0/REF
D1/REF
D2
D3
OUT
IN
V
REF
+
-
Figure 4 - GPIO Block Diagram
ZoomingADC™ for Pressure and Temperature Sensing
RegMode[1]
0
1
11
RegMode[0]
0
1
1
0
RegOut[4]
RegOut[5]
RegOut[6]
RegOut[7]
ZoomingADC
RegOut[0]
RegOut[2]
RegOut[3]
RegOut[1]
RegIn[0]
RegIn[2]
RegIn[3]
RegIn[1]
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