STPM11_08 STMICROELECTRONICS [STMicroelectronics], STPM11_08 Datasheet - Page 31

• Manufacturer Part Number: STPM11_08
• Description: Single phase energy metering IC with pulsed output and digital calibration
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Figure 21. Timing for writing configuration and mode bits
Any pin above has internal weak pull up device of nominal 15 A. This means that when a pin
is not forced by external signals, the state of the pin is logic high. A high state of any input
pin above is considered as an idle (not active) state. For the CFGI to operate correctly, the
STPM1x must be correctly supplied as described in the Power Supply section. When SCS is
active (low), signal SDA-TD should change its state at trailing edge of signal SCL-NLC and
the signal SDA-TD should be stable at the next leading edge of signal SCL-NLC. The first
valid bit of SDA-TD always starts with the activation of signal SCL-NLC.
Writing procedure
Each writable bit (Configuration and Mode bits) has its own 6-bit absolute address. For the
configuration bits, the 6-bit address value corresponds to its decimal value, while for the
mode bits, the addresses are the ones indicated in the Mode Signal paragraph (7.16).
In order to change the latch state, a byte of data must be sent to STPM1x via CFGI. This
byte consists of 1-bit data to be latched (msb), followed by 6-bit address of destination latch,
followed by 1-bit don't care data (lsb) which totals 8 bits of command byte.
For example, if we would like to set the configuration bit 52 (additional gain of 8) to 1, we
must convert the decimal 52 to its 6-bit binary value: 110100. The byte command will be
then composed like this:
1 bit DATA value+6-bits address+1 bit (0 or 1) as depicted in
binary command will be 11101000 (0xE8) or 11101001 (0xE9).
– SYN-NP: this pin allows synchronization of the communication between STPM1x and
– SCL-NLC: it is basically the clock pin of the CFGI interface. This pin function is also
– SDA-TD is the Data pin. SDA-TD is the input of the serial bit data signal.
when it is high. In this section, the SYN-NP, SCL-NLC and SDA-TD operation as part
of the CFGI interface is described.
the host. See
controlled by the SCS status. If SCS is low, SCL-NLC is the input of the serial bit
synchronization clock signal. When SCS is high, SCL-NLC is also high which
determines the idle state of the CFGI.
Figure 19
- for detailed timing of the pin.
Figure 19
-. In this case the
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