U6264ADC07 ETC [List of Unclassifed Manufacturers], U6264ADC07 Datasheet - Page 5

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U6264ADC07

Manufacturer Part Number
U6264ADC07
Description
STANDARD 8K X 8 SRAM
Manufacturer
ETC [List of Unclassifed Manufacturers]
Datasheet
Data Retention Mode E1-Controlled
December 12, 1997
4.5 V
0 V
Chip Deselect to Data Retention Time
Operating Recovery Time
Switching Characteristics
Time to Output in Low-Z
Cycle Time
Access Time
Pulse Widths
Setup Times
Data Hold Time
Address Hold from End of Write
Output Hold Time from Address
Change
V
V
Write Cycle Time
Read Cycle Time
E1 LOW or E2 HIGH to Data Valid
G LOW to Data Valid
Address to Data Valid
Write Pulse Width
Chip Enable to End of Write
Address Setup Time
Chip Enable to End of Write
Write Pulse Width
Data Setup Time
E1 HIGH or E2 LOW to Output in
High-Z
W LOW to Output in High-Z
G HIGH to Output in High-Z
2.2 V
E2(DR)
CC(DR)
- 0.2 V
V
t
DR
CC(DR)
V
- 0.2 V or V
Data Retention
V
E1(DR)
CC(DR)
2 V
V
CC(DR)
E2(DR)
+ 0.3 V
0.2 V
t
rec
t
t
t
HZWE
t
HZCE
HZOE
Alt.
t
t
t
t
t
t
t
t
t
t
ACE
t
t
t
t
WC
WP
CW
CW
WP
DH
AH
RC
OE
DS
OH
AA
AS
LZ
Symbol
2.2 V
t
t
DR
rec
V
E1
CC
:
5
:
t
t
t
t
t
t
t
t
t
dis(W)
t
t
t
dis(G)
IEC
t
t
su(W)
t
t
dis(E)
t(QX)
su(A)
su(E)
su(D)
t
w(W)
w(E)
t
a(E)
a(G)
a(A)
h(D)
h(A)
v(A)
cW
cR
4.5 V
0
Data Retention Mode E2-Controlled
min 0 ns
min t
0.8 V
07
70
70
50
65
65
50
35
5
0
0
0
5
0
0
0
-
-
-
cR
Min.
t
DR
100
100
10
70
90
90
70
40
5
0
0
0
5
0
0
0
-
-
-
Data Retention
V
V
E2(DR)
CC(DR)
07
10
70
40
70
25
30
25
0.2 V
2 V
Max.
100
100
10
10
50
35
35
35
t
rec
U6264A
0.8 V
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
E2
CC

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