U6264BDA07 ZMD [Zentrum Mikroelektronik Dresden AG], U6264BDA07 Datasheet

U6264BDA07

Manufacturer Part Number

U6264BDA07

Description

STANDARD 5K X 8 SRAM

Manufacturer

ZMD [Zentrum Mikroelektronik Dresden AG]

Datasheet

1.U6264BDA07.pdf (9 pages)

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April 20, 2004

Features

Pin Configuration

DQ0

DQ1

DQ2

8192 x 8 bit static CMOS RAM

70 ns Access Times

Common data inputs and

outputs

Three-state outputs

Typ. operating supply current

Standby current:

< 2 µA at T

Data retention current at 2 V:

< 1 µA at T

TTL/CMOS-compatible

Automatic reduction of power

dissipation in long Read or Write

cycles

Power supply voltage 5 V

Operating temperature ranges:

ESD protection > 2000 V

(MIL STD 883C M3015.7)

Latch-up immunity > 100 mA

Packages: PDIP28 (600 mil)

VSS

QS 9000 Quality Standard

A12

n.c.

70 ns: 10 mA

-40 to 85 °C

-40 to 125 °C

Top View

0 to 70 °C

PDIP

SOP

SOP28 (330 mil)

≤ 70 °C

VCC

W (WE)

E2 (CE2)

A11

G (OE)

A10

E1 (CE1)

DQ7

DQ6

DQ5

DQ4

DQ3

Description

The U6264B is a static RAM manu-

factured using a CMOS process

technology with the following ope-

rating modes:

- Read

- Write

The memory array is based on a

6-transistor cell.

The circuit is activated by the rising

edge of E2 (at E1 = L), or the falling

edge of E1 (at E2 = H). The

address and control inputs open

simultaneously. According to the

information of W and G, the data

inputs, or outputs, are active. In a

Read cycle, the data outputs are

activated by the falling edge of G,

afterwards the data word read will

be available at the outputs DQ0 -

DQ7. After the address change, the

data outputs go High-Z until the

new read information is available.

The data outputs have no preferred

state. If the memory is driven by

CMOS levels in the active state,

and if there is no change of the

- Standby

- Data Retention

Pin Description

Signal Name

A0 - A12

DQ0 - DQ7

VCC

VSS

n.c.

Signal Description

Address Inputs

Data In/Out

Chip Enable 1

Chip Enable 2

Output Enable

Write Enable

Power Supply Voltage

Ground

not connected

address, data input and control

signals W or G, the operating cur-

rent (at I

value of the operating current in the

Standby mode. The Read cycle is

finished by the falling edge of E2 or

W, or by the rising edge of E1,

respectively.

Data retention is guaranteed down

to 2 V. With the exception of E2, all

inputs consist of NOR gates, so

that no pull-up/pull-down resistors

are required. This gate circuit

allows

standby requirements by activation

with TTL-levels too.

If the circuit is inactivated by

E2 = L, the standby current (TTL)

drops to 150 µA typ.

Standard 8K x 8 SRAM

= 0 mA) drops to the

achieve

U6264B

low

power

Related parts for U6264BDA07

U6264BDA07 Summary of contents

Page 1

Features 8192 x 8 bit static CMOS RAM ! 70 ns Access Times ! Common data inputs and ! outputs Three-state outputs ! Typ. operating supply current ! 70 ns Standby current: ! < 2 µ ...

Page 2

U6264B Block Diagram A11 A12 A10 Address Change Detector E2 E1 Truth Table Operating Mode Standby/not selected Internal Read Read Write * Memory Cell Array 256 Rows ...

Characteristics All voltages are referenced (ground). SS All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of ...

Page 4

U6264B Electrical Characteristics Supply Current - Operating Mode Supply Current - Standby Mode (CMOS level) Supply Current - Standby Mode (TTL level) Supply Current - Data Retention Mode Output High Voltage Output Low Voltage Output High Current Output Low Current ...

Page 5

Switching Characteristics Time to Output in Low-Z Cycle Time Write Cycle Time Read Cycle Time Access Time E1 LOW or E2 HIGH to Data Valid G LOW to Data Valid Address to Data Valid Pulse Widths Write Pulse Width Chip ...

Page 6

U6264B Test Configuration for Functional Check measurement dis(E) dis(W) dis(G) Capacitance Input Capacitance Output Capacitance All pins not under test must be connected with ground by capacitors. Ordering ...

Page 7

Read Cycle 1 (during Read cycle Output Read Cycle 2 (during Read cycle Output Write Cycle 1 (W-controlled ...

Page 8

U6264B Write Cycle 2 (E1-controlled Input DQ i Output G Write Cycle 3 (E2-controlled Input DQ i Output G undefined The information describes the type of ...

Page 9

LIFE SUPPORT POLICY ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which ...

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