ADT7302_05 AD [Analog Devices], ADT7302_05 Datasheet - Page 4

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ADT7302_05

Manufacturer Part Number
ADT7302_05
Description
Manufacturer
AD [Analog Devices]
Datasheet
ADT7302
TIMING CHARACTERISTICS
Guaranteed by design and characterization, not production tested. All input signals are specified with t
and timed from a voltage level of 1.6 V.
T
Table 2.
Parameter
t
t
t
t
t
t
t
t
1
2
1
2
3
4
5
6
7
8
See Figure 14 for the SPI timing diagram.
Measured with the load circuit of Figure 2.
A
2
2
= T
MIN
to T
1
MAX
, V
DD
= 2.7 V to 5.25 V, unless otherwise noted.
Limit
5
25
25
35
20
5
5
40
Figure 2. Load Circuit for Data Access Time and Bus Relinquish Time
OUTPUT
PIN
TO
50pF
C
L
Unit
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns max
Rev. 0 | Page 4 of 16
200μA
200μA
I
I
OL
OH
1.6V
Comments
CS to SCLK Setup Time
SCLK High Pulse Width
SCLK Low Pulse Width
Data Access Time After SCLK Falling Edge
Data Setup Time Prior to SCLK Rising Edge
Data Hold Time After SCLK Rising Edge
CS to SCLK Hold Time
CS to DOUT High Impedance
R
= t
F
= 5 ns (10% to 90% of V
DD
)

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