ADT7320UCPZ AD [Analog Devices], ADT7320UCPZ Datasheet - Page 4

• Manufacturer Part Number: ADT7320UCPZ
• Manufacturer: AD [Analog Devices]

ADT7320
1
2
3
4
5
SPI TIMING SPECIFICATIONS
T
(10% to 90% of V
Table 2.
Parameter
t
t
t
t
t
t
t
t
t
t
1
2
3
4
1
2
3
4
5
6
7
8
9
10
Accuracy includes repeatability.
The equivalent three-sigma limits are ±0.15°C. This three-sigma specification is provided to enable comparison with other vendors who use these limits.
For higher accuracy at 5 V operation, contact an Analog Devices, Inc., sales representative.
Based on a floating average of 10 readings.
Drift includes solder heat resistance (SHR) and lifetime tests performed as per JEDEC Standard JESD22-A108.
Sample tested during initial release to ensure compliance. All input signals are specified with t
See Figure 2.
SCLK active edge is falling edge of SCLK.
This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading
capacitances.
A
4
Shutdown Current
Power Dissipation Normal Mode
Power Dissipation 1 SPS
= −40°C to +150°C, V
At 3.3 V
At 5.5 V
1, 2
DOUT
SCLK
DIN
CS
DD
) and timed from a voltage level of 1.6 V.
Limit at T
0
100
100
30
25
0
60
80
10
80
0
0
60
80
10
DD
= 2.7 V to 5.5 V, unless otherwise noted. All input signals are specified with rise time (t
t
t
9
1
MIN
t
4
MSB
, T
t
t
1
2
5
MAX
(B Version)
2
t
3
2.0
4.4
700
150
3
Figure 2. Detailed SPI Timing Diagram
Rev. PrA | Page 4 of 24
15
25
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns max
ns max
ns min
μA
μA
μW
μW
7
Conditions/Comments
CS falling edge to SCLK active edge setup time
SCLK high pulse width
SCLK low pulse width
Data valid to SCLK edge setup time
Data valid to SCLK edge hold time
SCLK active edge to data valid delay
V
V
Bus relinquish time after CS inactive edge
CS rising edge to SCLK edge hold time
CS falling edge to DOUT active time
V
V
SCLK inactive edge to DOUT high
Supply current in shutdown mode
Supply current in shutdown mode
V
Power dissipated for V
DD
DD
DD
DD
R
DD
= t
LSB
= 4.5 V to 5.5 V
= 2.7 V to 3.6 V
= 4.5 V to 5.5 V
= 2.7 V to 3.6 V
8
= 3.3 V, normal mode at 25°C
F
= 5 ns (10% to 90% of V
MSB
1
t
6
Preliminary Technical Data
2
DD
= 3.3 V, T
DD
7
) and timed from a voltage level of 1.6 V.
LSB
A
= 25°C
t
t
8
10
8
3
t
R
7
) = fall time (t
3
F
) = 5 ns