ADUC842BCP AD [Analog Devices], ADUC842BCP Datasheet - Page 5

• Manufacturer Part Number: ADUC842BCP
• Description: 12- Bit ADCs and DACs with Embedded Hi-Speed 62KB FLASH MCU
• Manufacturer: AD [Analog Devices]

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Specifications subject to change without notice.
unbuffered mode.
ADC Linearity is guaranteed during normal MicroConverter Core operation.
Based on external ADC system components the user may need to execute a system calibration to remove additional external channel errors
SNR calculation includes distortion and noise components.
Flash/EE Memory Reliability Characteristics apply to both the Flash/EE program memory and the Flash/EE data memory.
or erase cycle.
Temperature Range -40ºC to +85ºC.
ADC LSB Size = Vref / 2^12 i.e for Internal Vref=2.5V, 1LSB = 610uV and for External Vref =1V, 1LSB = 244uV.
Offset and Gain Error and Offset and Gain Error Match are measured after factory calibration.
and achieve these specifications.
Channel to Channel Crosstalk is measured on adjacent channels.
The Temperature Monitor will give a measure of the die temperature directly, air temperature can be inferred from this result.
These numbers are not production tested but are guaranteed by Design and/or Characterization data on production release.
DAC linearity is calculated using :
DAC Differential NonLinearity specified on 0 to Vref
DAC specification for output impedance in the unbuffered case depends on DAC code
Measured with Vref and Cref pins decoupled with 0.1µF capacitors to graound. Power-up time for the Internal Reference will be determined
Endurance is qualified to 100 Kcycles as per JEDEC Std. 22 method A117 and measured at -40ºC, +25ºC, and +85ºC, typical endurance at
Retention lifetime equivalent at junction temperature (Tj) = 55ºC as per JEDEC Std. 22 method A117. Retention lifetime based on an
D
When using an External Reference device, the internal bandgap reference input can be bypassed by setting the ADCCON1.6 bit. In this
Power Supply current consumption is measured in Normal, Idle, and Power-Down Modes under the following conditions:
by the value of the decoupling capacitor chosen for both the Vref and Cref pins.
mode the Vref and Cref pins need to be shorted together for correct operation.
25ºC is 700 Kcycles.
activation energy of 0.6eV will derate with junction temperature as shown in Figure 27 in the Flash/EE Memory description section of this
data sheet.
DAC specifications for Isink, voltage output settling time and digital-to-analog glitch engergy depend on external buffer implementation in
VDD
reduced code range of 48 to 4095, 0 to Vref range.
reduced code range of 48 to 3945, 0 to V
DAC Output Load = 10K Ohms and 100 pF.
power supply current will increase typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program
Normal Mode:
Idle Mode:
Power-Down Mode: Reset = 0.4 V, All Port 0 pins = 0.4 V, All other digital I/O and Port 1 pins are open circuit, Core Clk changed
Reset = 0.4 V, Digital I/O pins = open circuit,
software
Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, PCON.0=1, Core
Execution suspended in idle mode.
via CD bits in PLLCON, PCON.0=1,
OSC_PD bit (PLLCON.7) in PLLCON SFR
loop.
DD
range.
and 0 to Vdd ranges
Core Execution suspended inpower-down mode, OSC turned ON or OFF via
– 5 –
Core Clk changed via CD bits in PLLCON, Core Executing internal
ADuC842