FIN3385_12 FAIRCHILD [Fairchild Semiconductor], FIN3385_12 Datasheet - Page 17
FIN3385_12
Manufacturer Part Number
FIN3385_12
Description
Low-Voltage, 28-Bit, Flat-Panel Display Link Serializer / Deserializer
Manufacturer
FAIRCHILD [Fairchild Semiconductor]
Datasheet
1.FIN3385_12.pdf
(21 pages)
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© 2003 Fairchild Semiconductor Corporation
FIN3385 / FIN3386 • Rev. 1.0.6
AC Loadings and Waveforms
Note:
24. t
The minimum and maximum pulse position values are based on the bit position of each of the seven bits within
the LVDS data stream across PVT (Process, Voltage Supply, and Temperature).
RSKM
is the budget for the cable skew and source clock skew plus Inter-Symbol Interference (ISI).
Figure 20. Transmitter Output Pulse Bit Position
Figure 22. Receiver LVDS Input Skew Margin
Figure 21. Receiver Input Bit Position
(Continued)
17
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